专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08044490B2 Semiconductor device including fuse 有权
标题翻译：半导体装置包括保险丝
公开(公告)号：US08044490B2
公开(公告)日：2011-10-25
申请号：US12502490
申请日：2009-07-14
申请人： Seung-woo Shin , Byung-lyul Park , Jong-myeong Lee , Gil-heyun Choi , Jong-ho Yun
发明人： Seung-woo Shin , Byung-lyul Park , Jong-myeong Lee , Gil-heyun Choi , Jong-ho Yun
IPC分类号： H01L29/00 , H01L27/10
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.
摘要翻译：提供了一种包括保险丝的半导体器件，其中防止在保险丝或金属布线周围的绝缘层由于保险丝的切断而被损坏，这在维修过程中可能发生。半导体器件包括形成在半导体层上的导电线，形成在导电线上的保护层，与导电线电连接的一个或多个保险丝，以及形成在一个或多个保险丝上的保险丝保护层，除了保护层。

2. 发明申请

US20100193902A1 SEMICONDUCTOR DEVICE INCLUDING FUSE 有权
标题翻译：包括保险丝的半导体器件
公开(公告)号：US20100193902A1
公开(公告)日：2010-08-05
申请号：US12502490
申请日：2009-07-14
申请人： Seung-woo SHIN , Byung-Iyul Park , Jong-myeong Lee , Gil-heyun Choi , Jong-ho Yun
发明人： Seung-woo SHIN , Byung-Iyul Park , Jong-myeong Lee , Gil-heyun Choi , Jong-ho Yun
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.
摘要翻译：提供了一种包括保险丝的半导体器件，其中防止在保险丝或金属布线周围的绝缘层由于保险丝的切断而被损坏，这在维修过程中可能发生。半导体器件包括形成在半导体层上的导电线，形成在导电线上的保护层，与导电线电连接的一个或多个保险丝，以及形成在一个或多个保险丝上的保险丝保护层，除了保护层。

3. 发明授权

US07842600B2 Methods of forming interlayer dielectrics having air gaps 有权
标题翻译：形成具有气隙的层间电介质的方法
公开(公告)号：US07842600B2
公开(公告)日：2010-11-30
申请号：US12364598
申请日：2009-02-03
申请人： Jong-ho Yun , Jong-Myeong Lee , Gil-heyun Choi
发明人： Jong-ho Yun , Jong-Myeong Lee , Gil-heyun Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76849 , H01L2224/05026 , H01L2224/05639 , H01L2224/05669 , H01L2224/13 , H01L2924/00014 , H01L2224/05099
摘要： Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap.
摘要翻译：提供了形成具有气隙的层间电介质的方法，包括在半导体衬底上形成第一绝缘层。第一绝缘层限定沟槽。在沟槽中形成金属线，使得金属线在第一绝缘层的上表面下方凹入。在金属线上形成金属层，其中金属层包括填充凹部的覆盖层部分，形成在覆盖层部分上的上部，和形成在与沟槽相邻的第一绝缘层的部分上的突出部分从上部侧向突出。去除第一绝缘层，并且在半导体衬底上形成覆盖金属层的第二绝缘层，由此在金属层的伸出部分的下方形成气隙。去除第二绝缘层的一部分以露出金属层的上部。去除金属层的上部和外伸部分。在半导体基板上形成第三绝缘层，从该基板上去除上部和外伸部分以保持气隙。

4. 发明申请

US20090298282A1 Methods of Forming Interlayer Dielectrics Having Air Gaps 有权
标题翻译：形成具有空气间隙的层间电介质的方法
公开(公告)号：US20090298282A1
公开(公告)日：2009-12-03
申请号：US12364598
申请日：2009-02-03
申请人： Jong-Ho Yun , Jong-Myeong Lee , Gil-heyun Choi
发明人： Jong-Ho Yun , Jong-Myeong Lee , Gil-heyun Choi
IPC分类号： H01L21/60
CPC分类号： H01L21/7682 , H01L21/76849 , H01L2224/05026 , H01L2224/05639 , H01L2224/05669 , H01L2224/13 , H01L2924/00014 , H01L2224/05099
摘要： Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap.
摘要翻译：提供了形成具有气隙的层间电介质的方法，包括在半导体衬底上形成第一绝缘层。第一绝缘层限定沟槽。在沟槽中形成金属线，使得金属线在第一绝缘层的上表面下方凹入。在金属线上形成金属层，其中金属层包括填充凹部的覆盖层部分，形成在覆盖层部分上的上部，和形成在与沟槽相邻的第一绝缘层的部分上的突出部分从上部侧向突出。去除第一绝缘层，并且在半导体衬底上形成覆盖金属层的第二绝缘层，由此在金属层的伸出部分的下方形成气隙。去除第二绝缘层的一部分以露出金属层的上部。去除金属层的上部和外伸部分。在半导体基板上形成第三绝缘层，从该基板上去除上部和外伸部分以保持气隙。

5. 发明授权

US08021980B2 Methods of manufacturing semiconductor devices including a copper-based conductive layer 有权
标题翻译：制造包括铜基导电层的半导体器件的方法
公开(公告)号：US08021980B2
公开(公告)日：2011-09-20
申请号：US12753196
申请日：2010-04-02
申请人： Youngseok Kim , Jong-ho Yun , Kwang-jin Moon , Gil-heyun Choi , Jong-myeong Lee , Zung-sun Choi , Hye-Kyung Jung
发明人： Youngseok Kim , Jong-ho Yun , Kwang-jin Moon , Gil-heyun Choi , Jong-myeong Lee , Zung-sun Choi , Hye-Kyung Jung
IPC分类号： H01L21/44
CPC分类号： H01L21/7684 , H01L21/02068 , H01L21/02074 , H01L21/76849 , H01L21/76861 , H01L21/76883
摘要： Provided are methods of manufacturing semiconductor devices. The methods may include forming a first insulation layer on a semiconductor substrate, forming a groove by selectively etching the first insulation layer, filling the groove with a copper-based conductive layer, depositing a cobalt-based capping layer on the copper-based conductive layer by electroless plating, and cleansing the first insulation layer and the cobalt-based capping layer using a basic cleansing solution.
摘要翻译：提供制造半导体器件的方法。所述方法可以包括在半导体衬底上形成第一绝缘层，通过选择性蚀刻第一绝缘层形成沟槽，用铜基导电层填充沟槽，在铜基导电层上沉积钴基覆盖层通过无电解电镀，并且使用基本清洁溶液清洁第一绝缘层和钴基覆盖层。

6. 发明申请

US20100255676A1 Methods of Manufacturing Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100255676A1
公开(公告)日：2010-10-07
申请号：US12753196
申请日：2010-04-02
申请人： Youngseok Kim , Jong-ho Yun , Kwang-jin Moon , Gil-heyun Choi , Jong-myeong Lee , Zung-sun Choi , Hye-Kyung Jung
发明人： Youngseok Kim , Jong-ho Yun , Kwang-jin Moon , Gil-heyun Choi , Jong-myeong Lee , Zung-sun Choi , Hye-Kyung Jung
IPC分类号： H01L21/3205
CPC分类号： H01L21/7684 , H01L21/02068 , H01L21/02074 , H01L21/76849 , H01L21/76861 , H01L21/76883
摘要： Provided are methods of manufacturing semiconductor devices. The methods may include forming a first insulation layer on a semiconductor substrate, forming a groove by selectively etching the first insulation layer, filling the groove with a copper-based conductive layer, depositing a cobalt-based capping layer on the copper-based conductive layer by electroless plating, and cleansing the first insulation layer and the cobalt-based capping layer using a basic cleansing solution.
摘要翻译：提供制造半导体器件的方法。所述方法可以包括在半导体衬底上形成第一绝缘层，通过选择性蚀刻第一绝缘层形成沟槽，用铜基导电层填充沟槽，在铜基导电层上沉积钴基覆盖层通过无电解电镀，并且使用基本清洁溶液清洁第一绝缘层和钴基覆盖层。

7. 发明申请

US20110003476A1 METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING LANDING PADS FORMED BY ELECTROLESS PLATING 有权
标题翻译：形成半导体器件的方法，包括通过电镀镀层形成的引线垫
公开(公告)号：US20110003476A1
公开(公告)日：2011-01-06
申请号：US12829776
申请日：2010-07-02
申请人： Jong-ho Yun , Gil-heyun Choi , Jong-myeong Lee
发明人： Jong-ho Yun , Gil-heyun Choi , Jong-myeong Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76895 , H01L21/288 , H01L21/76807 , H01L21/76834 , H01L21/76879
摘要： A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad.
摘要翻译：可以减少由于金属接触和插塞之间的未对准而导致金属接触和插塞之间的接触电阻Rc增大的半导体器件，并且可以减少在形成插头的过程中Cu填充过程的困难。半导体器件包括：衬底，其包括有源区和器件隔离层; 金属接触件，其形成在所述基板上并电连接到所述有源区域; 通过无电镀形成在金属接触件上的着陆垫; 以及形成在所述着陆板上并且经由所述着陆垫电连接到所述金属接触件的插头。

8. 发明授权

US08497207B2 Methods of forming semiconductor devices including landing pads formed by electroless plating 有权
标题翻译：形成半导体器件的方法，包括通过无电镀形成的着陆焊盘
公开(公告)号：US08497207B2
公开(公告)日：2013-07-30
申请号：US12829776
申请日：2010-07-02
申请人： Jong-ho Yun , Gil-heyun Choi , Jong-myeong Lee
发明人： Jong-ho Yun , Gil-heyun Choi , Jong-myeong Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/76895 , H01L21/288 , H01L21/76807 , H01L21/76834 , H01L21/76879
摘要： A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad.
摘要翻译：可以减少由于金属接触和插塞之间的未对准而导致金属接触和插塞之间的接触电阻Rc增大的半导体器件，并且可以减少在形成插头的过程中Cu填充过程的困难。半导体器件包括：衬底，其包括有源区和器件隔离层; 金属接触件，其形成在所述基板上并电连接到所述有源区域; 通过无电镀形成在金属接触件上的着陆垫; 以及形成在所述着陆板上并且经由所述着陆垫电连接到所述金属接触件的插头。

9. 发明授权

US08354308B2 Conductive layer buried-type substrate, method of forming the conductive layer buried-type substrate, and method of fabricating semiconductor device using the conductive layer buried-type substrate 有权
标题翻译：导电层掩埋型基板，形成导电层掩埋型基板的方法以及使用导电层掩埋型基板制造半导体器件的方法
公开(公告)号：US08354308B2
公开(公告)日：2013-01-15
申请号：US13221158
申请日：2011-08-30
申请人： Pil-kyu Kang , Gil-heyun Choi , Dae-lok Bae , Byung-lyul Park , Dong-kak Lee
发明人： Pil-kyu Kang , Gil-heyun Choi , Dae-lok Bae , Byung-lyul Park , Dong-kak Lee
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/66666 , H01L21/76254 , H01L21/84 , H01L27/10814 , H01L27/10876 , H01L27/10894 , H01L27/1203
摘要： A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.
摘要翻译：公开了一种导电层掩埋型衬底。基板包括结合到支撑基板的硅氧化层，形成在硅氧化层上的粘合促进层，并且改善硅氧化层和导电层之间的粘附性，其中导电层形成在粘附促进层上并且包括金属层和形成在导电层上的单晶半导体层。

10. 发明授权

US08884440B2 Integrated circuit device including through-silicon via structure having offset interface 有权
标题翻译：集成电路器件包括具有偏移接口的通硅通孔结构
公开(公告)号：US08884440B2
公开(公告)日：2014-11-11
申请号：US13603978
申请日：2012-09-05
申请人： Su-kyoung Kim , Gil-heyun Choi , Byung-lyul Park , Kwang-jin Moon , Kun-sang Park , Dong-chan Lim , Do-sun Lee
发明人： Su-kyoung Kim , Gil-heyun Choi , Byung-lyul Park , Kwang-jin Moon , Kun-sang Park , Dong-chan Lim , Do-sun Lee
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40 , H01L23/538 , H01L21/768 , H01L25/065 , H01L23/498
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/49827 , H01L25/0657 , H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.
摘要翻译：集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分表面至少到第二通孔。还描述了相关的制造方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式