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1. 发明申请

US20100148819A1 Majority voter circuits and semiconductor device including the same 审中-公开
标题翻译：多数选民电路和半导体器件包括相同
公开(公告)号：US20100148819A1
公开(公告)日：2010-06-17
申请号：US12656590
申请日：2010-02-04
申请人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-II Park
发明人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-II Park
IPC分类号： H03K19/23 , H03K19/20
CPC分类号： H03K19/23
摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
摘要翻译：多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

2. 发明授权

US07688102B2 Majority voter circuits and semiconductor devices including the same 有权
标题翻译：多数选民电路和半导体器件包括相同
公开(公告)号：US07688102B2
公开(公告)日：2010-03-30
申请号：US11819600
申请日：2007-06-28
申请人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
发明人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
IPC分类号： H03K19/003
CPC分类号： H03K19/23
摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
摘要翻译：多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

3. 发明申请

US20080001626A1 Majority voter circuits and semiconductor devices including the same 有权
标题翻译：多数选民电路和半导体器件包括相同
公开(公告)号：US20080001626A1
公开(公告)日：2008-01-03
申请号：US11819600
申请日：2007-06-28
申请人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
发明人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
IPC分类号： H03K19/23
CPC分类号： H03K19/23
摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
摘要翻译：多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

4. 发明申请

US20140019833A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20140019833A1
公开(公告)日：2014-01-16
申请号：US14031620
申请日：2013-09-19
申请人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

5. 发明授权

US08004328B2 AC-coupling phase interpolator and delay-locked loop using the same 失效
标题翻译：交流耦合相位内插器和使用其的延迟锁定环路
公开(公告)号：US08004328B2
公开(公告)日：2011-08-23
申请号：US12570186
申请日：2009-09-30
申请人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

6. 发明申请

US20100079180A1 AC-COUPLING PHASE INTERPOLATOR AND DELAY-LOCKED LOOP USING THE SAME 失效
标题翻译：交流耦合相位插补器和延迟锁定环使用相同
公开(公告)号：US20100079180A1
公开(公告)日：2010-04-01
申请号：US12570186
申请日：2009-09-30
申请人： JIN-GOOK KIM , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： JIN-GOOK KIM , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/00 , H03H11/16
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

7. 发明申请

US20110242916A1 ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：接通终端电路，数据输出缓冲器和半导体存储器件
公开(公告)号：US20110242916A1
公开(公告)日：2011-10-06
申请号：US13048219
申请日：2011-03-15
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-II Park , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-II Park , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C7/00 , H03K19/003
CPC分类号： H03K19/018585 , G06F2213/0038 , G11C5/063 , G11C7/1051 , G11C7/1057 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要翻译：片上终端电路包括连接到外部引脚的终端电阻单元和连接到终端电阻单元的终端控制单元。终端电阻单元为连接到外部引脚的传输线提供终端阻抗。终端控制单元响应于与数据速率相关联的多个强度码位改变终端阻抗。

8. 发明授权

US07541947B2 Semiconductor devices, a system including semiconductor devices and methods thereof 有权
公开(公告)号：US07541947B2
公开(公告)日：2009-06-02
申请号：US11802886
申请日：2007-05-25
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
IPC分类号： H03M7/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

9. 发明申请

US20090097339A1 Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands 有权
标题翻译：具有内部命令生成器的集成电路存储器件，其中支持使用独立和相关命令的扩展命令集
公开(公告)号：US20090097339A1
公开(公告)日：2009-04-16
申请号：US12236978
申请日：2008-09-24
申请人： Young-soo Sohn , Kwang-II Park , Seung-Jun Bae
发明人： Young-soo Sohn , Kwang-II Park , Seung-Jun Bae
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1072 , G11C7/22 , G11C8/18
摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.
摘要翻译：集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

10. 发明申请

US20070206428A1 HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
标题翻译：高速相位调整数据速率（QDR）收发器及其方法
公开(公告)号：US20070206428A1
公开(公告)日：2007-09-06
申请号：US11612800
申请日：2006-12-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
摘要翻译：提供了一种高速双倍或正交数据速率接口半导体器件及其方法。用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和第二组（字节）数据。发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

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