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1. 发明申请

US20090008696A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME 失效
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20090008696A1
公开(公告)日：2009-01-08
申请号：US12168799
申请日：2008-07-07
申请人： Seung-Jin YANG , Jeong-Uk HAN , Yong-Suk CHOI , Hyok-Ki KWON , Bae-Seong KWON
发明人： Seung-Jin YANG , Jeong-Uk HAN , Yong-Suk CHOI , Hyok-Ki KWON , Bae-Seong KWON
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7885 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.
摘要翻译：根据一个实施例，半导体存储器件的一般特征可以包括在半导体衬底上的栅极绝缘层，栅极绝缘层上的浮动栅极和设置在浮动栅极一侧的字线。面对字线的浮动栅极的第一侧可以包括朝向字线突出的突出部分。突出部分的尖端可以包括相对于半导体衬底的顶表面基本垂直地延伸的角部。

2. 发明申请

US20090278192A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090278192A1
公开(公告)日：2009-11-12
申请号：US12433971
申请日：2009-05-01
申请人： Yong-Suk CHOI , Jeong-Uk HAN , Yong-Tae KIM , Seung-Jin YANG , Hyok-Ki KWON
发明人： Yong-Suk CHOI , Jeong-Uk HAN , Yong-Tae KIM , Seung-Jin YANG , Hyok-Ki KWON
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/4234 , H01L29/66833
摘要： A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is formed on the substrate and extends up onto and covers the charge trapping layer pattern. The gate surrounds an upper portion of the charge trapping layer pattern so as to face towards and upper surface and opposite side surfaces of the charge trapping layer pattern.
摘要翻译：半导体器件包括隧道绝缘层图案，电荷俘获层图案，阻挡层图案和栅极结构。隧道绝缘层图案形成在基板上。电荷俘获层图案形成在隧道绝缘层图案上。阻挡层图案形成在基板上并向上延伸并覆盖电荷捕获层图案。栅极围绕电荷俘获层图案的上部，以面向电荷俘获层图案的上表面和相对的侧表面。

3. 发明申请

US20080283873A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080283873A1
公开(公告)日：2008-11-20
申请号：US12117630
申请日：2008-05-08
申请人： Seung-Jin YANG , Jeong-Uk HAN , Yong-Tae KIM , Yong-Suk CHOI , Hyok-Ki KWON
发明人： Seung-Jin YANG , Jeong-Uk HAN , Yong-Tae KIM , Yong-Suk CHOI , Hyok-Ki KWON
IPC分类号： H01L27/115 , H01L21/8247 , H01L21/4763
CPC分类号： H01L27/105 , H01L21/76898 , H01L21/8221 , H01L23/485 , H01L27/0688 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.
摘要翻译：半导体器件具有第一半导体层，包括第一电路，设置在第一半导体层上并具有第二电路的第二半导体层，以及延伸穿过第一和第二半导体层的部分的通孔，并且第一半导体层和第二电路电连接。电路中的一个是逻辑电路，另一个电路是存储器电路。半导体器件通过在各个衬底上制造逻辑电路和存储器电路的晶体管，堆叠衬底以及将逻辑电路和存储器电路与通孔电连接来制造。

4. 发明申请

US20100059888A1 Mask ROM and method of fabricating the same 审中-公开
标题翻译：掩模ROM及其制造方法
公开(公告)号：US20100059888A1
公开(公告)日：2010-03-11
申请号：US12590482
申请日：2009-11-09
申请人： Yong-Kyu Lee , Hee-Seog JEON , Jeong-Uk HAN , Young-Ho Kim , Myung-Jo Chun
发明人： Yong-Kyu Lee , Hee-Seog JEON , Jeong-Uk HAN , Young-Ho Kim , Myung-Jo Chun
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L27/1021
摘要： A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.
摘要翻译：掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示第二种类型的存储单元。多个第二导电线中的每一个形成在二极管的列上。

5. 发明申请

US20080308875A1 MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：掩蔽ROM器件，包括掩模ROM器件的半导体器件，以及制造掩模ROM器件和半导体器件的方法
公开(公告)号：US20080308875A1
公开(公告)日：2008-12-18
申请号：US12132148
申请日：2008-06-03
申请人： Yong-Kyu LEE , Jeong-Uk HAN , Hee-Seog JEON , Young-Ho KIM , Myung-Jo CHUN , Jung-Ho MOON
发明人： Yong-Kyu LEE , Jeong-Uk HAN , Hee-Seog JEON , Young-Ho KIM , Myung-Jo CHUN , Jung-Ho MOON
IPC分类号： H01L27/118 , H01L21/8238
CPC分类号： H01L27/105 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L27/1052 , H01L27/11266 , H01L27/11293
摘要： A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.
摘要翻译：可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。离子电池包括在衬底上的离子栅极结构和衬底内的离子阱结结构。单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

6. 发明申请

US20080029808A1 NON-VOLATILE MEMORY AND METHOD OF FABRICATING SAME 失效
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20080029808A1
公开(公告)日：2008-02-07
申请号：US11837361
申请日：2007-08-10
申请人： Hee-Seog JEON , Seung-Beom YOON , Jeong-Uk HAN
发明人： Hee-Seog JEON , Seung-Beom YOON , Jeong-Uk HAN
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.
摘要翻译：在一个实施例中，半导体器件包括具有第一结区域和第二结区域的半导体衬底。绝缘浮栅设置在基板上。浮置栅极至少部分地与第一结区重叠。在浮动门上设置绝缘的程序门。程序门具有弯曲的上表面。半导体器件还包括布置在衬底上并与浮动栅极相邻的绝缘擦除栅极。擦除栅极部分地与第二结区重叠。

7. 发明申请

US20080014691A1 MASK ROM CELL, NOR-TYPE MASK ROM DEVICE, AND RELATED METHODS OF FABRICATION 审中-公开
标题翻译：掩模ROM单元，NOR型掩模ROM设备和相关的制造方法
公开(公告)号：US20080014691A1
公开(公告)日：2008-01-17
申请号：US11774724
申请日：2007-07-09
申请人： Hee-Seog JEON , Jeong-Uk HAN
发明人： Hee-Seog JEON , Jeong-Uk HAN
IPC分类号： H01L21/8234
CPC分类号： H01L27/105 , H01L21/823418 , H01L27/1052 , H01L27/112 , H01L27/11266 , H01L27/11293
摘要： A mask read-only memory (ROM) cell, a method for fabricating the mask ROM cell, a NOR-type mask ROM device, and a method for fabricating the NOR-type mask ROM device are disclosed. A mask ROM cell includes a substrate including an ON cell region and an OFF cell region, a first gate electrode disposed in the ON cell region, and a second gate electrode disposed in the OFF cell region. The mask ROM cell also includes a first impurity region disposed in the substrate proximate a sidewall of the first gate electrode, wherein a portion of the first impurity region is disposed under the first gate electrode; and a second impurity region disposed the substrate proximate a sidewall of the second gate electrode, wherein no portion of the second impurity region is disposed under the second gate electrode.
摘要翻译：公开了一种掩模只读存储器（ROM）单元，用于制造掩模ROM单元的方法，NOR型掩模ROM器件和用于制造NOR型掩模ROM器件的方法。掩模ROM单元包括包括ON单元区域和OFF单元区域的基板，设置在ON单元区域中的第一栅极电极和设置在OFF单元区域中的第二栅电极。掩模ROM单元还包括靠近第一栅电极的侧壁设置在基板中的第一杂质区，其中第一杂质区的一部分设置在第一栅电极下方; 以及第二杂质区域，其将所述基板设置在所述第二栅电极的侧壁附近，其中所述第二杂质区域的部分没有设置在所述第二栅电极下方。

8. 发明申请

US20080012062A1 EEPROM DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译： EEPROM装置及其制造方法
公开(公告)号：US20080012062A1
公开(公告)日：2008-01-17
申请号：US11775871
申请日：2007-07-11
申请人： Hyun-Khe YOO , Jeong-Uk HAN , Hee-Seog JEON , Sung-Gon CHOI , Bo-young SEO , Chang-Min JEON , Ji-Do RYU
发明人： Hyun-Khe YOO , Jeong-Uk HAN , Hee-Seog JEON , Sung-Gon CHOI , Bo-young SEO , Chang-Min JEON , Ji-Do RYU
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： An electrically erasable programmable read-only memory (EEPROM) device includes an EEPROM cell located on a semiconductor substrate, the EEPROM cell including a memory transistor and a selection transistor. A source region and a drain region are located on the semiconductor substrate adjacent to opposite sides of the EEPROM cell, respectively, and a floating region is positioned between the memory transistor and the selection transistor. The source region includes a first doped region, a second doped region and a third doped region, where the first doped region surrounds a bottom surface and sidewalls of the second doped region, and the second doped surrounds a bottom surface and sidewalls of the third doped region. Also, a second impurity concentration of the second doped region is higher than that of the first doped region and lower than that of the third doped region.
摘要翻译：电可擦除可编程只读存储器（EEPROM）装置包括位于半导体衬底上的EEPROM单元，EEPROM单元包括存储晶体管和选择晶体管。源极区域和漏极区域分别位于与EEPROM单元的相对侧相邻的半导体衬底上，并且浮置区域位于存储晶体管和选择晶体管之间。源极区域包括第一掺杂区域，第二掺杂区域和第三掺杂区域，其中第一掺杂区域围绕第二掺杂区域的底表面和侧壁，第二掺杂区域包围底表面和第三掺杂区域的侧壁地区。此外，第二掺杂区域的第二杂质浓度高于第一掺杂区域的第二杂质浓度，并且低于第三掺杂区域的第二杂质浓度。

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