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1. 发明授权

US06940302B1 Integrated circuit output driver circuitry with programmable preemphasis 有权
标题翻译：具有可编程预加重功能的集成电路输出驱动器电路
公开(公告)号：US06940302B1
公开(公告)日：2005-09-06
申请号：US10338921
申请日：2003-01-07
申请人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
发明人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
IPC分类号： H03K19/0185 , H03K19/177 , H04L25/02 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H04L25/0272 , H04L25/0286
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
摘要翻译：提供了具有差分I / O电路的可编程逻辑器件集成电路。差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

2. 发明授权

US07307446B1 Integrated circuit output driver circuitry with programmable preemphasis 有权
标题翻译：具有可编程预加重功能的集成电路输出驱动器电路
公开(公告)号：US07307446B1
公开(公告)日：2007-12-11
申请号：US11510514
申请日：2006-08-24
申请人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
发明人： Sergey Y. Shumarayev , Thomas H. White , Rakesh H. Patel , Wilson Wong
IPC分类号： H03K17/16
CPC分类号： H03K19/018585 , H03K5/06 , H03K5/13 , H03K5/151 , H03K2005/00032 , H03K2005/00065
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
摘要翻译：提供了具有差分I / O电路的可编程逻辑器件集成电路。差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

3. 发明授权

US6107854A Variable speed path circuit and method 失效
标题翻译：变速路径电路及方法
公开(公告)号：US6107854A
公开(公告)日：2000-08-22
申请号：US62379
申请日：1998-04-17
申请人： Wilson Wong , John E. Turner , Thomas H. White , Rakesh H Patel
发明人： Wilson Wong , John E. Turner , Thomas H. White , Rakesh H Patel
IPC分类号： H03K5/00 , H03K19/003 , H03K19/017 , H03K19/0185 , H03H11/26
CPC分类号： H03K19/00384 , H03K19/01721 , H03K19/018585 , H03K2005/00078
摘要： A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.
摘要翻译：速度路径电路包括参考电路和可调节的驱动部件，其可以被接通或关断以改变速度路径，以便满足电路的最小延迟规范。在一个实施例中，使用一个或多个差分放大器来检测示例电路元件的强度并产生参考信号。可选实施例包括用于断开参考电路以避免任何直流电流消耗的机构。本发明可以用于广泛的集成电路中，并且还可以用在可编程逻辑器件（PLD）中。参考电路可以通过使用可编程逻辑元件与电源断开连接。

4. 发明授权

US06985010B2 Integrated circuit devices with power supply detection circuitry 失效
公开(公告)号：US06985010B2
公开(公告)日：2006-01-10
申请号：US10753056
申请日：2004-01-06
申请人： Sergey Y. Shumarayev , Thomas H. White
发明人： Sergey Y. Shumarayev , Thomas H. White
IPC分类号： H03K19/003
CPC分类号： H03K17/22 , G06F1/24 , G06F1/28
摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

5. 发明授权

US06737885B1 Integrated circuit devices with power supply detection circuitry 有权
标题翻译：具有电源检测电路的集成电路器件
公开(公告)号：US06737885B1
公开(公告)日：2004-05-18
申请号：US10327284
申请日：2002-12-20
申请人： Sergey Y. Shumarayev , Thomas H. White
发明人： Sergey Y. Shumarayev , Thomas H. White
IPC分类号： H03K19003
CPC分类号： H03K17/22 , G06F1/24 , G06F1/28
摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.
摘要翻译：提供集成电路装置，其包括指示电源是否达到功能电压电平的功率检测电路。功率检测电路包括耦合到电源的锁存器，其可以检测所有电源是否已经达到功能电压电平，逻辑电路以提供适当的输出信号，以及向电力检测电路提供电流的阱偏置电路。良好的偏置电路提供来自第一电源的电流以达到功能电压电平，使得可以从功率检测电路提供指示，而不需要所有电源的功能电压电平。来自功率检测电路的输出可以与控制信号组合，用于各种应用。应用包括将集成电路器件置于复位状态，直到电源达到功能电压电平。

6. 发明授权

US06549032B1 Integrated circuit devices with power supply detection circuitry 有权
标题翻译：具有电源检测电路的集成电路器件
公开(公告)号：US06549032B1
公开(公告)日：2003-04-15
申请号：US09935186
申请日：2001-08-22
申请人： Sergey Y. Shumarayev , Thomas H. White
发明人： Sergey Y. Shumarayev , Thomas H. White
IPC分类号： H03K19003
CPC分类号： H03K17/22 , G06F1/24 , G06F1/28
摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.
摘要翻译：提供集成电路装置，其包括指示电源是否达到功能电压电平的功率检测电路。功率检测电路包括耦合到电源的锁存器，其可以检测所有电源是否已经达到功能电压电平，逻辑电路以提供适当的输出信号，以及向电力检测电路提供电流的阱偏置电路。良好的偏置电路提供来自第一电源的电流以达到功能电压电平，使得可以从功率检测电路提供指示，而不需要所有电源的功能电压电平。来自功率检测电路的输出可以与控制信号组合，用于各种应用。应用包括将集成电路器件置于复位状态，直到电源达到功能电压电平。

7. 发明授权

US06515507B1 Control pin for specifying integrated circuit voltage levels 有权
标题翻译：用于指定集成电路电压电平的控制引脚
公开(公告)号：US06515507B1
公开(公告)日：2003-02-04
申请号：US09607569
申请日：2000-06-29
申请人： Rakesh H. Patel , Thomas H. White
发明人： Rakesh H. Patel , Thomas H. White
IPC分类号： G06F738
CPC分类号： G11C16/30 , G11C5/147 , G11C16/20 , H03K3/011 , H03K3/0315
摘要： An integrated circuit has one or more external control pins to control and indicate which of two or more different VCC or other voltage levels will be used. The control pin receives a logic signal, high or low, and draws zero static power. A user can use the integrated circuit with two or more VCC voltage levels by indicating which voltage level at the control pins. In a specific embodiment, the integrated circuit has nonvolatile memory cells such as EEPROM or Flash cells that a configurable and reconfigurable using on-chip programming circuitry. The programming circuitry may generate and use superhigh or high voltages, higher than the VCC voltage.
摘要翻译：集成电路具有一个或多个外部控制引脚，用于控制并指示将使用两个或多个不同VCC或其他电压电平中的哪一个。控制引脚接收高或低的逻辑信号，并绘制零静态功率。用户可以通过指示控制引脚上的哪个电压电平，使用具有两个或多个VCC电压电平的集成电路。在具体实施例中，集成电路具有非易失性存储单元，例如EEPROM或闪存单元，其是使用片上编程电路的可配置和可重新配置的。编程电路可以产生和使用高于VCC电压的超高电压或高电压。

8. 发明授权

US6137313A Resistive pull-up device for I/O pin 失效
标题翻译：用于I / O引脚的电阻上拉装置
公开(公告)号：US6137313A
公开(公告)日：2000-10-24
申请号：US80539
申请日：1998-05-18
申请人： Wilson Wong , Thomas H. White
发明人： Wilson Wong , Thomas H. White
IPC分类号： H03K19/00 , H03K19/003 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/00315 , H03K19/0013 , H03K19/09429
摘要： Various embodiments for improved I/O pin pull-up circuitry are disclosed. The pull-up devices according to the present invention minimize dissipation of crowbar current when the I/O pin is tri-stated. Circuit techniques are disclosed for minimizing the crowbar current as well as making the circuit high voltage tolerant.
摘要翻译：公开了用于改进的I / O引脚上拉电路的各种实施例。当I / O引脚为三态时，根据本发明的上拉器件使撬棒电流的耗散最小化。公开了用于最小化撬棒电流以及使电路具有高电压容限的电路技术。

9. 发明授权

US08432724B2 Memory elements with soft error upset immunity 有权
标题翻译：内存元件具有软错误的不安定性
公开(公告)号：US08432724B2
公开(公告)日：2013-04-30
申请号：US12753809
申请日：2010-04-02
申请人： Thomas H. White
发明人： Thomas H. White
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C11/4125 , G11C11/419
摘要： Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity.
摘要翻译：提供具有存储单元的集成电路。存储单元可以具有以环形配置连接的四个逆变器状电路和四个对应的存储节点。四个逆变器状电路可以形成存储单元的存储部分。一些逆变器状电路可以在上拉和下拉路径中具有三态晶体管。三态晶体管可以由地址信号控制。地址和存取晶体管可以耦合在一些存储节点和数据线之间。地址和存取晶体管可用于读写存储单元。在写操作期间，可以断言地址信号以关闭三态晶体管并消除来自该单元的竞争电流。在读取和正常操作期间，可以将地址信号置为无效，以允许类似逆变器的电路保持电池的当前状态，同时提供软错误不耐受性。

10. 发明申请

US20120032276A1 N-WELL/P-WELL STRAP STRUCTURES 有权
标题翻译： N-WELL / P-WELL STRAP STRUCTURES
公开(公告)号：US20120032276A1
公开(公告)日：2012-02-09
申请号：US12851805
申请日：2010-08-06
申请人： Dustin Do , Andy Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
发明人： Dustin Do , Andy Lee , Giles V. Powell , Bradley Jensen , Swee Aun Lau , Wuu-Cherng Lin , Thomas H. White
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L21/823493 , H01L21/32055 , H01L21/76224 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L29/7833
摘要： Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
摘要翻译：公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带而获得较低的空间要求。

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