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1. 发明授权

US07629213B2 Method of manufacturing flash memory device with void between gate patterns 有权
标题翻译：制造在栅极图案之间具有空隙的闪存器件的方法
公开(公告)号：US07629213B2
公开(公告)日：2009-12-08
申请号：US11647628
申请日：2006-12-29
申请人： Whee Won Cho , Jung Geun Kim , Seong Hwan Myung , Cheol Mo Jeong
发明人： Whee Won Cho , Jung Geun Kim , Seong Hwan Myung , Cheol Mo Jeong
IPC分类号： H01L21/8238
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.
摘要翻译：一种制造闪速存储器件的方法包括以下步骤：在半导体衬底上形成用于单元的栅极图案和用于选择晶体管的栅极图案，在包含栅极图案的所得表面上形成缓冲绝缘层，形成绝缘层以形成空隙用于单元的栅极图案之间的间隔，在绝缘层上形成氮化物层，并且通过间隔物蚀刻工艺在用于选择晶体管的每个栅极图案的一侧上形成间隔物。

2. 发明申请

US20080102622A1 Method of forming metal line in semiconductor device 审中-公开
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20080102622A1
公开(公告)日：2008-05-01
申请号：US11647088
申请日：2006-12-27
申请人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho , Seong Hwan Myung
发明人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho , Seong Hwan Myung
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a formation of an oxide layer on an aluminum layer caused by a slurry and cleaning solution used in the chemical mechanical polishing (CMP) process and carry out an uniform polishing process, whereby it is possible to prevent a digging phenomenon on a metal layer from being generated.
摘要翻译：一种在半导体器件中形成金属线的方法，包括以下步骤：在通过镶嵌工艺形成金属线时，通过使用非金属材料在虚拟区域上形成虚拟图案的半导体器件中形成金属线以防止由化学机械抛光（CMP）工艺中使用的浆料和清洗液在铝层上形成氧化物层，并进行均匀的抛光工艺，从而可以防止在金属层上的挖掘现象从被生成。

3. 发明授权

US07521319B2 Method of forming gate of flash memory device 失效
标题翻译：形成闪存器件门的方法
公开(公告)号：US07521319B2
公开(公告)日：2009-04-21
申请号：US11646777
申请日：2006-12-28
申请人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
发明人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.
摘要翻译：一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。

4. 发明申请

US20080003754A1 Method of forming gate of flash memory device 失效
标题翻译：形成闪存器件门的方法
公开(公告)号：US20080003754A1
公开(公告)日：2008-01-03
申请号：US11646777
申请日：2006-12-28
申请人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
发明人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.
摘要翻译：一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。

5. 发明申请

US20080003745A1 Method of manufacturing a flash memory device 审中-公开
标题翻译：制造闪存装置的方法
公开(公告)号：US20080003745A1
公开(公告)日：2008-01-03
申请号：US11646860
申请日：2006-12-28
申请人： Seong Hwan Myung , Jung Geun Kim , Whee Won Cho , Cheol Mo Jeong
发明人： Seong Hwan Myung , Jung Geun Kim , Whee Won Cho , Cheol Mo Jeong
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： The present invention relates to a method of manufacturing a flash memory device. The method includes the steps of forming cell gate patterns and select transistor gate patterns on a semiconductor substrate; forming a low dielectric layer on the resultant structure; etching the low dielectric layer, leavinin gaps adjacent the cell gate patterns; and, forming a nitride layer spacer on one side wall of each of the select transistor gate patterns. The resulting flash memory device has an improved rate of change in the threshold voltage and reduces the contact resistance when a self-aligned contact method is subsequently performed.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。该方法包括在半导体衬底上形成单元栅极图案和选择晶体管栅极图案的步骤; 在所得结构上形成低介电层; 蚀刻低介电层，与细胞栅极图案相邻的叶绿素间隙; 并且在每个选择晶体管栅极图案的一个侧壁上形成氮化物层间隔物。所产生的闪速存储器件在随后执行自对准接触方法时具有改善的阈值电压变化率并降低接触电阻。

6. 发明授权

US07897504B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07897504B2
公开(公告)日：2011-03-01
申请号：US11747444
申请日：2007-05-11
申请人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho , Seong Hwan Myung
发明人： Jung Geun Kim , Cheol Mo Jeong , Whee Won Cho , Seong Hwan Myung
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28273
摘要： A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.
摘要翻译：一种制造半导体器件的方法，其中可以防止在具有拉伸应力的蚀刻层上形成非晶碳膜而发生提升现象。根据本发明，由于可以减小蚀刻层或非晶碳膜上的压缩应力，或者在蚀刻层或非晶碳膜之间形成压缩应力膜，以防止发生升降现象，因此可以是其他图案形成以制造高度集成的半导体器件。

7. 发明申请

US20080003724A1 Method of manufacturing flash memory device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US20080003724A1
公开(公告)日：2008-01-03
申请号：US11647628
申请日：2006-12-29
申请人： Whee Won Cho , Jung Geun Kim , Seong Hwan Myung , Cheol Mo Jeong
发明人： Whee Won Cho , Jung Geun Kim , Seong Hwan Myung , Cheol Mo Jeong
IPC分类号： H01L21/8232
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.
摘要翻译：一种制造闪速存储器件的方法包括以下步骤：在半导体衬底上形成用于单元的栅极图案和用于选择晶体管的栅极图案，在包含栅极图案的所得表面上形成缓冲绝缘层，形成绝缘层以形成空隙用于单元的栅极图案之间的间隔，在绝缘层上形成氮化物层，并且通过间隔物蚀刻工艺在用于选择晶体管的每个栅极图案的一侧上形成间隔物。

8. 发明申请

US20080268608A1 METHOD OF FABRICATING A FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪速存储器件的方法
公开(公告)号：US20080268608A1
公开(公告)日：2008-10-30
申请号：US11951926
申请日：2007-12-06
申请人： Suk Joong Kim , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
发明人： Suk Joong Kim , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
IPC分类号： H01L21/76
CPC分类号： H01L27/11521
摘要： In a method of fabricating a flash memory device, after an isolation trench is formed, a bottom surface and sidewalls of the trench are gap-filled with a HARP film having a favorable step coverage. A wet etch process is performed such that the HARP film remains on the sidewalls of a tunnel dielectric layer, thereby forming a wing spacer. Accordingly, the tunnel dielectric layer can be protected and an interference phenomenon can be reduced because a control gate to be formed subsequently is located between floating gates.
摘要翻译：在制造闪速存储器件的方法中，在形成隔离沟槽之后，沟槽的底表面和侧壁间隙填充有具有良好阶梯覆盖率的HARP膜。执行湿蚀刻工艺，使得HARP膜保留在隧道介电层的侧壁上，从而形成翼间隔物。因此，由于随后要形成的控制栅极位于浮置栅极之间，所以可以保护隧道介质层并且可以减小干扰现象。

9. 发明授权

US07652352B2 Active structure of a semiconductor device 有权
标题翻译：半导体器件的主动结构
公开(公告)号：US07652352B2
公开(公告)日：2010-01-26
申请号：US11771484
申请日：2007-06-29
申请人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
发明人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
IPC分类号： H01L29/06
CPC分类号： H01L21/76229 , H01L29/0657
摘要： An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.
摘要翻译：半导体器件的有源结构。一方面，半导体器件的有源结构包括与第一至第（n）场区域交替形成的第一至第（n）场区域和第一至第（n + 1）个有源区域，其中一个或多个第一至第（n + 1）个有源区域在其边缘部分连接以封闭一个或多个场区域。另一方面，半导体器件的有源结构包括与第一至第（n）场区域交替形成的第一至第（n）场区域和第一至第（n + 1）个有源区域，其中第一和第 n + 1）个有源区域在其边缘部分连接到第（n + 2）个和第（n + 3）个有效区域，关闭场区域。

10. 发明申请

US20080224272A1 Active Structure of a Semiconductor Device 有权
标题翻译：半导体器件的有源结构
公开(公告)号：US20080224272A1
公开(公告)日：2008-09-18
申请号：US11771484
申请日：2007-06-29
申请人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
发明人： Whee Won Cho , Seong Hwan Myung , Eun Jung Ko
IPC分类号： H01L29/06
CPC分类号： H01L21/76229 , H01L29/0657
摘要： An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein one or more of the first to (n+1)th active regions are connected at edge portions thereof to close one or more of the field regions. In another aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th field regions, wherein the first and (n+1)th active regions are connected to (n+2)th and (n+3)th active regions at edge portions thereof, closing the field regions.
摘要翻译：半导体器件的有源结构。一方面，半导体器件的有源结构包括第一至第（N）个第场区域，以及与第一至第（N + 1）个第一至第（n）个第场区域，其中第一至第（n + 1）个第个有源区域中的一个或多个在其边缘部分连接以封闭一个或多个的领域地区。另一方面，半导体器件的有源结构包括第一至第（n）场区域，以及与第一至（n）个有源区域连接到第（n + 2）个第和第（n + 3）个区域，在其边缘部分处有效区域，关闭场区域。

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