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    • 3. 发明授权
    • Bus arbitration system, medium, and method
    • 总线仲裁系统,媒介和方法
    • US07886097B2
    • 2011-02-08
    • US11812946
    • 2007-06-22
    • Seok-yoon JungIl-san KimJin-hong ParkTack-don Han
    • Seok-yoon JungIl-san KimJin-hong ParkTack-don Han
    • G06F13/40
    • G06F13/364
    • A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.
    • 总线仲裁系统,媒介和方法。 总线仲裁系统可以仲裁访问多个主机的总线,请求使用至少一个从机连接到的总线,并且可以包括总线使用许可单元,其输出多个总线授权信号以授予 使用总线到同时请求使用总线的多个主机,同时处理可用信号选择单元从多个操作指令信号中选择预定数量的具有预定相似度的操作指令信号 以及响应于总线许可信号从主机输入的操作指令单元,以及通过总线同时将所选择的操作指令信号发送到从机的操作指令单元。
    • 4. 发明申请
    • Bus arbitration system, medium, and method
    • 总线仲裁系统,媒介和方法
    • US20080005435A1
    • 2008-01-03
    • US11812946
    • 2007-06-22
    • Seok-yoon JungIl-san KimJin-hong ParkTack-don Han
    • Seok-yoon JungIl-san KimJin-hong ParkTack-don Han
    • G06F13/00
    • G06F13/364
    • A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.
    • 总线仲裁系统,媒介和方法。 总线仲裁系统可以仲裁访问多个主机的总线,请求使用至少一个从机连接到的总线,并且可以包括总线使用许可单元,其输出多个总线授权信号以授予 使用总线到同时请求使用总线的多个主机,同时处理可用信号选择单元从多个操作指令信号中选择预定数量的具有预定相似度的操作指令信号 以及响应于总线许可信号从主机输入的操作指令单元,以及通过总线同时将所选择的操作指令信号发送到从机的操作指令单元。
    • 5. 发明授权
    • Pixel cache, 3D graphics accelerator using the same, and method therefor
    • 像素缓存,3D图形加速器使用相同,及其方法
    • US07042462B2
    • 2006-05-09
    • US10731434
    • 2003-12-10
    • Jae-hyun KimYong-je KimTack-don HanWoo-chan ParkGil-hwan LeeIl-san Kim
    • Jae-hyun KimYong-je KimTack-don HanWoo-chan ParkGil-hwan LeeIl-san Kim
    • G09G5/36G06T15/40
    • G06T15/005G06T15/405
    • An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.
    • 提供了用于三维(3D)图形加速器的像素高速缓存的有效结构。 像素高速缓存包括z数据存储单元,其从帧存储器读取z数据,并将读取的z数据提供给像素光栅化管线; 以及彩色数据存储单元,其在z数据存储单元从帧存储器读取z数据的同时,预先从帧存储器读取和存储颜色数据,并且仅将颜色数据提供给像素光栅化管线 当预定的z检验的结果被确定为在像素光栅化管线中成功时。 因此,在处理彩色数据之前,像素高速缓存结构仅能够预先读取和存储需要的颜色数据,从而防止访问等待时间,提高彩色高速缓存的效率,并降低功耗。