专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US12101945B2 Semiconductor device 有权
公开(公告)号：US12101945B2
公开(公告)日：2024-09-24
申请号：US18225186
申请日：2023-07-24
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tomoaki Atsumi , Shuhei Nagatsuka , Tamae Moriwaka , Yuta Endo
IPC分类号： H10B69/00 , G11C7/16 , G11C8/14 , G11C11/24 , G11C11/403 , G11C11/408 , H01L27/06 , H01L29/24 , H01L29/786 , H10B41/20 , H10B41/70
CPC分类号： H10B69/00 , G11C7/16 , G11C8/14 , G11C11/24 , G11C11/403 , G11C11/4085 , H01L27/0688 , H01L29/24 , H01L29/7869 , H10B41/20 , H10B41/70
摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

2. 发明申请

US20200211627A1 Semiconductor Device and Method for Driving Semiconductor Device 审中-公开
公开(公告)号：US20200211627A1
公开(公告)日：2020-07-02
申请号：US16732555
申请日：2020-01-02
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tomoaki Atsumi , Junpei Sugao
IPC分类号： G11C11/4094 , H01L29/786 , H01L27/12 , G11C11/4096 , G11C11/401 , G11C11/4097
摘要： The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

3. 发明授权

US10109371B2 Test method of semiconductor device 有权
公开(公告)号：US10109371B2
公开(公告)日：2018-10-23
申请号：US15391929
申请日：2016-12-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tomoaki Atsumi , Shuhei Nagatsuka , Kazuaki Ohshima
IPC分类号： G11C11/22 , G11C29/50 , G11C11/4096 , H01L27/108
摘要： The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

4. 发明授权

US09990965B2 Storage device 有权
公开(公告)号：US09990965B2
公开(公告)日：2018-06-05
申请号：US13709196
申请日：2012-12-10
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tomoaki Atsumi
IPC分类号： G11C5/06 , G11C7/06 , G11C11/4091 , G11C11/4097 , G11C5/02
CPC分类号： G11C7/06 , G11C5/02 , G11C11/4091 , G11C11/4097
摘要： Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit.

5. 发明申请

US20170004865A1 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权
标题翻译：半导体器件，电子元件和电子器件
公开(公告)号：US20170004865A1
公开(公告)日：2017-01-05
申请号：US15125658
申请日：2015-03-05
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Shuhei Nagatsuka , Tomoaki Atsumi , Shunpei Yamazaki
IPC分类号： G11C7/22 , G11C5/14
CPC分类号： G11C7/22 , G11C5/14 , G11C11/405 , G11C11/565 , G11C27/005 , H01L27/0688 , H01L27/088 , H01L27/108 , H01L27/1156 , H01L27/1225 , H01L29/786
摘要： A semiconductor device which can write and read multilevel data is provided. Anode connecting a source or a drain of an OS transistor and a gate of an OS transistor can hold the distribution of a plurality of potentials. A circuit configuration is employed in which the potential of the node is changed by capacitive coupling to control a conduction state of the OS transistor whose gate is connected thereto so that the potential of a gate of a Si transistor is changed. The potential of the gate of the Si transistor is changed positively in accordance with the potential change by capacitive coupling and is changed negatively in accordance with another transistor. In accordance with a change in value of current flowing through the Si transistor is detected, written data is read.
摘要翻译：提供了可以写入和读取多级数据的半导体器件。连接OS晶体管的源极或漏极和OS晶体管的栅极的阳极可以保持多个电位的分布。采用电路结构，其中通过电容耦合来改变节点的电位，以控制其栅极连接到其上的OS晶体管的导通状态，使得Si晶体管的栅极的电位改变。 Si晶体管的栅极的电位根据电容耦合的电位变化而正向变化，并根据另一个晶体管呈负变化。根据检测到流过Si晶体管的电流值的变化，读取写入的数据。

6. 发明授权

US09294126B2 Cyclic redundancy check circuit and semiconductor device having the cyclic redundancy check circuit 有权
公开(公告)号：US09294126B2
公开(公告)日：2016-03-22
申请号：US14679148
申请日：2015-04-06
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Masafumi Ito , Tomoaki Atsumi
IPC分类号： H03M13/00 , H03M13/09 , H04B1/10
CPC分类号： H03M13/09 , H04B1/10
摘要： An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

7. 发明授权

US08942029B2 Memory device 有权
公开(公告)号：US08942029B2
公开(公告)日：2015-01-27
申请号：US13705587
申请日：2012-12-05
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tomoaki Atsumi , Takashi Okuda
IPC分类号： G11C11/24 , G11C8/08 , H01L27/02 , H01L27/108 , H01L27/12 , G11C11/404 , G11C11/4097
摘要： A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.

8. 发明授权

US08791461B2 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US08791461B2
公开(公告)日：2014-07-29
申请号：US14037778
申请日：2013-09-26
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tomoaki Atsumi , Hiroki Inoue
IPC分类号： H01L29/10
CPC分类号： H01L21/02683 , H01L21/02532 , H01L21/2026 , H01L27/1255 , H01L27/1285 , H01L27/1296 , H01L28/40
摘要： In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.
摘要翻译：在包括数字电路部分和具有设置在基板上的电容器部分的模拟电路部分的半导体器件中，电容器部分设置有第一布线，第二布线和多个具有多个电容器元件的块。此外，设置在每个块中的多个电容器元件中的每一个具有半导体膜，该半导体膜具有第一杂质区和设置有分隔开第一杂质区的多个第二杂质区，并且在第一杂质区上设置有导电膜，绝缘膜。由第一杂质区，绝缘膜和导电膜形成电容器。

9. 发明申请

US20140108836A1 MICROCONTROLLER AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：微控制器及其制造方法
公开(公告)号：US20140108836A1
公开(公告)日：2014-04-17
申请号：US14055200
申请日：2013-10-16
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuji Nishijima , Hidetomo Kobayashi , Tomoaki Atsumi , Kiyoshi Kato , Shunpei Yamazaki
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3206 , G06F1/3243 , G06F1/3275 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.
摘要翻译：提供以低功耗模式工作的微控制器。微控制器包括CPU，存储器和诸如定时器电路的外围电路。外围电路中的寄存器设置在与总线线路的接口中。提供用于控制电源控制的电源门。微控制器不仅可以在所有电路都有效的正常工作模式下工作，而且还可以在一些电路处于活动状态的低功耗模式下工作。在诸如CPU的寄存器的寄存器中提供易失性存储器和非易失性存储器。在电源停止之前，易失性存储器中的数据被备份在非易失性存储器中。在操作模式返回到正常模式的情况下，当再次开始供电时，非易失性存储器中的数据被写回到易失性存储器中。

10. 发明申请

US20140014964A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140014964A1
公开(公告)日：2014-01-16
申请号：US14026369
申请日：2013-09-13
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Satoshi Murakami , Yosuke Tsukamoto , Tomoaki Atsumi , Masayuki Sakakura
IPC分类号： H01L29/04
CPC分类号： H01L29/04 , G02F1/13454 , G02F1/136204 , H01L27/12 , H01L27/1214 , H01L27/124
摘要： In a semiconductor device, gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.
摘要翻译：在半导体器件中，栅极信号线在结晶半导体膜之上彼此间隔开。因此，当在层间绝缘膜中打开接触孔时，第一保护电路不电连接。在干蚀刻期间产生的用于打开接触孔的静电从栅极信号线移动，损坏栅极绝缘膜，通过晶体半导体膜，并且在栅极绝缘膜到达栅极信号线之前再次损坏栅极绝缘膜。由于在干蚀刻期间产生的静电损害第一保护电路，所以静电的能量减小，直到损失驱动电路TFT的能力。从而防止了驱动电路TFT遭受静电放电损坏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式