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    • 3. 发明授权
      US06489652B1 Trench DMOS device having a high breakdown resistance 失效
    • Trench DMOS device having a high breakdown resistance
    • 具有高耐击穿性的沟槽DMOS器件
    • US06489652B1
    • 2002-12-03
    • US08742754
    • 1996-11-01
    • Chang-Ki Jeon , Young-Soo Jang
    • Chang-Ki Jeon , Young-Soo Jang
    • H01L2976
    • H01L29/7813 , H01L29/42368
    • A trench DMOS device having improved breakdown characteristics. The trench DMOS device has a gate oxide layer which has a substantially flattened thick portion in the bottom of the trench and which is relatively thinner on the sidewalls. In greater detail, the trench DMOS device comprises a trench formed in a semiconductor substrate, said trench having sidewalls and a bottom, a gate polysilicon layer filled into said trench, and a gate oxide layer formed between said gate polysilicon layer and the sidewalls and bottom of said trench, wherein a bottom part of said gate oxide layer has a thickness greater than both sidewall parts thereof, and a central region of said bottom part is substantially flattened with a thickness greater than boundary regions thereof. Also disclosed is a novel method of fabricating a trench DMOS device.
    • 具有改进的击穿特性的沟槽DMOS器件。 沟槽DMOS器件具有栅极氧化物层，其在沟槽的底部具有基本平坦的厚部分，并且在侧壁上相对较薄。 更详细地，沟槽DMOS器件包括形成在半导体衬底中的沟槽，所述沟槽具有侧壁和底部，填充到所述沟槽中的栅极多晶硅层以及形成在所述栅极多晶硅层与侧壁和底部之间的栅极氧化物层 的所述沟槽，其中所述栅极氧化物层的底部具有大于其两个侧壁部分的厚度，并且所述底部部分的中心区域大致平坦化，其厚度大于其边界区域。 还公开了一种制造沟槽DMOS器件的新颖方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5804476A Method of forming BiCMOS devices having mosfet and bipolar sections therein 失效
    • Method of forming BiCMOS devices having mosfet and bipolar sections therein
    • 在其中形成具有mosfet和双极部分的BiCMOS器件的方法
    • US5804476A
    • 1998-09-08
    • US758848
    • 1996-12-02
    • Young-Soo Jang
    • Young-Soo Jang
    • H01L27/06 , H01L21/265 , H01L21/8249 , H01L29/772 , H01L21/8238
    • H01L21/8249 , Y10S148/009 , Y10S148/124
    • A BiCMOS device and a manufacturing method thereof according to the present invention has a gate insulating layer of NMOSFET having non-uniform thickness. The thickness of the end portion of the gate insulating layer, which is near LDD regions, is thicker than that of center portion. Therefore, the GIDL and the gate-drain overlap capacitance is reduced. In addition, in case of the bipolar transistor of the BiCMOS device, there exists a portion of an oxide film below the side portion of the emitter polysilicon and over the side portions of the emitter region. Since this structure serves as a gate of field effect transistor, N- channel is produced in the emitter region when the emitter-base junction is reversely biased and thus the hot carrier reliability is improved.
    • 根据本发明的BiCMOS器件及其制造方法具有不均匀厚度的NMOSFET栅极绝缘层。 靠近LDD区域的栅极绝缘层的端部的厚度比中心部的厚度厚。 因此，GIDL和栅 - 漏重叠电容减小。 此外，在BiCMOS器件的双极晶体管的情况下，在发射极多晶硅的侧部和发射极区的侧部之上存在氧化膜的一部分。 由于该结构用作场效应晶体管的栅极，当发射极 - 基极结反向偏置时，在发射极区域中产生N沟道，因此提高了热载流子的可靠性。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5643810A Methods of forming BiCMOS semiconductor devices 失效
    • Methods of forming BiCMOS semiconductor devices
    • 形成BiCMOS半导体器件的方法
    • US5643810A
    • 1997-07-01
    • US688998
    • 1996-08-01
    • Young-Soo Jang
    • Young-Soo Jang
    • H01L21/334 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L21/265
    • H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S438/92
    • Methods of forming BiCMOS semiconductor devices include steps for forming bird's beak shaped oxide extensions between the gate electrodes and drain and source regions of CMOS devices to inhibit drain leakage currents and reduce gate-to-drain capacitance. These methods also include steps for forming bird's beak shaped oxide extensions at the emitter-base junctions of BJTs to reduce hot carrier induced P-N junction breakdown. A preferred method includes the steps of forming a gate electrode of a field effect transistor on a face of a semiconductor substrate and then forming self-aligned source and drain regions in the substrate using the gate electrode as a mask. A first conductive layer is then formed on the source and drain regions and used to diffuse dopants into the source and drain regions to increase the conductivity therein. Simultaneously with this diffusion step, the ends of the gate electrode and the first conductive layer are oxidized to form first bird's beak shaped oxide extensions between the gate electrode and the source and drain regions. These first bird's beak shaped oxide extensions are preferably formed to reduce drain leakage currents and gate-to-source capacitance by, among other things, reducing the electric field between the drain-side end of the gate electrode and the drain region. The first conductive layer can also be etched back into discrete intermediate source and drain contact regions to facilitate the subsequent formation of source and drain electrodes in electrical contact with the source and drain regions. Similar steps can also be performed to simultaneously form bipolar junction transistors adjacent the field effect transistors.
    • 形成BiCMOS半导体器件的方法包括在CMOS器件的栅极电极和漏极和源极区域之间形成鸟嘴形氧化物延伸的步骤，以抑制漏极漏电流并降低栅极 - 漏极电容。 这些方法还包括在BJT的发射极 - 基极结处形成鸟喙状氧化物延伸的步骤，以减少热载体诱导的P-N结击穿。 优选的方法包括以下步骤：在半导体衬底的表面上形成场效应晶体管的栅极，然后使用栅电极作为掩模在衬底中形成自对准的源区和漏区。 然后在源极和漏极区域上形成第一导电层，并且用于将掺杂剂扩散到源极和漏极区域中以增加其中的导电性。 与该扩散步骤同时，栅电极和第一导电层的端部被氧化，以在栅电极和源漏区之间形成第一鸟喙形氧化物延伸。 这些第一鸟喙形氧化物延伸部优选地被形成为通过减少栅极电极和漏极区域的漏极侧端部之间的电场来减少漏极漏电流和栅极至源极电容。 第一导电层还可以被回蚀刻成离散的中间源极和漏极接触区域，以便随后形成与源极和漏极区域电接触的源极和漏极。 也可以执行类似的步骤以同时形成与场效应晶体管相邻的双极结型晶体管。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5707721A Methods of forming field effect transistors having oxidation-controlled gate lengths 失效
    • Methods of forming field effect transistors having oxidation-controlled gate lengths
    • 形成具有氧化控制栅极长度的场效应晶体管的方法
    • US5707721A
    • 1998-01-13
    • US711047
    • 1996-09-10
    • Young-Soo Jang
    • Young-Soo Jang
    • H01L21/336 , H01L29/423 , H01L29/78
    • H01L29/6659 , H01L29/42376 , H01L29/7833 , H01L29/7834
    • Methods of forming field effect transistors having oxidation-controlled gate lengths include the steps of forming an insulated gate electrode on a face of semiconductor substrate. The gate electrode has exposed ends thereof which define an initial gate length. Source and drain region dopants are then implanted into first portions of the face, using the insulated gate electrode as an implant mask. The implanted first portions of the face and the exposed ends of the insulated gate electrode are then thermally oxidized to form a relatively thick oxide layer. During this step, the implanted dopants are diffused and bird's beak oxide extensions are formed at the upper and bottom corners of the gate electrode. The bird's beak oxide extensions are preferably formed to increase the separation distance between the gate electrode and the source and drain regions and thereby reduce the gate-source/drain capacitance and inhibit parasitic hot electron injection from the drain region. The step of thermally oxidizing the exposed ends of the insulated gate electrode also causes the ends to be consumed and the first portions of the face to become recessed. Thus, during oxidation, the length of the gate electrode can be reduced in a controlled manner and the degree of vertical overlap between the gate electrode and the diffused source and drain region dopants can be reduced to obtain a further reduction in the parasitic gate-source/drain capacitance. In addition, gate lengths having sub-micron dimensions can be achieved without requiring sub-micron photolithographic line widths to define the gate electrode.
    • 形成具有氧化控制的栅极长度的场效应晶体管的方法包括在半导体衬底的表面上形成绝缘栅电极的步骤。 栅电极具有限定初始栅极长度的露出端。 然后使用绝缘栅电极作为植入物掩模将源区和漏区掺杂剂注入到面的第一部分中。 然后，将表面的注入的第一部分和绝缘栅电极的暴露端热氧化以形成相对较厚的氧化物层。 在该步骤期间，注入的掺杂剂被扩散，并且在栅电极的上角和下角形成鸟喙氧化物延伸部。 鸟嘴状氧化物延伸部优选地形成为增加栅极电极和源极区域与漏极区域之间的间隔距离，从而减小栅极 - 源极/漏极电容并且抑制从漏极区域发出的寄生热电子注入。 热氧化绝缘栅电极的露出端的步骤也使得端部被消耗，并且面部的第一部分变得凹陷。 因此，在氧化期间，可以以受控的方式减小栅电极的长度，并且可以减小栅电极和扩散源极和漏区掺杂剂之间的垂直重叠程度，以进一步减小寄生栅极源 /漏极电容。 此外，可以实现具有亚微米尺寸的栅极长度，而不需要亚微米光刻线宽度来限定栅电极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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