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1. 发明授权

US08981484B2 Ballast resistor for super-high-voltage devices 有权
标题翻译：用于超高压设备的镇流电阻
公开(公告)号：US08981484B2
公开(公告)日：2015-03-17
申请号：US13467666
申请日：2012-05-09
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
IPC分类号： H01L23/62 , H01L29/78 , H01L29/66 , H01L29/08
CPC分类号： H01L27/0266 , H01L27/0288 , H01L29/0847 , H01L29/0878 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).
摘要翻译：一种集成电路（IC），包括具有第一掺杂级的IC的阱区和植入阱区的多个半导体区。多个半导体区域中的每一个具有第二掺杂水平。第二掺杂水平大于第一掺杂水平。多个多晶硅区域布置在多个半导体区域上。多晶硅区域分别连接到半导体区域。多个半导体区域是金属氧化物半导体场效应晶体管（MOSFET）的漏极。

2. 发明申请

US20120326234A1 BALLAST RESISTOR FOR SUPER-HIGH-VOLTAGE DEVICES 有权
标题翻译：用于超高压装置的压阻电阻器
公开(公告)号：US20120326234A1
公开(公告)日：2012-12-27
申请号：US13467666
申请日：2012-05-09
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0266 , H01L27/0288 , H01L29/0847 , H01L29/0878 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).
摘要翻译：一种集成电路（IC），包括具有第一掺杂级的IC的阱区和植入阱区的多个半导体区。多个半导体区域中的每一个具有第二掺杂水平。第二掺杂水平大于第一掺杂水平。多个多晶硅区域布置在多个半导体区域上。多晶硅区域分别连接到半导体区域。多个半导体区域是金属氧化物半导体场效应晶体管（MOSFET）的漏极。

3. 发明申请

US20120313692A1 SUPER-HIGH-VOLTAGE RESISTOR ON SILICON 审中-公开
标题翻译：硅超级高压电阻
公开(公告)号：US20120313692A1
公开(公告)日：2012-12-13
申请号：US13467648
申请日：2012-05-09
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
IPC分类号： G05F3/02
CPC分类号： H01L28/20 , H01L27/0676 , H01L27/0794
摘要： An integrated circuit (IC) including a first layer of a conducting material; a second layer of an insulating material, where the second layer has a first side arranged adjacent to the first layer, and a second side; and a substrate arranged adjacent to the second side of the second layer. A first well arranged in the substrate. The first well is adjacent to the second side of the second layer. The substrate and the first well have opposite doping.
摘要翻译：一种包括导电材料的第一层的集成电路（IC）绝缘材料的第二层，其中所述第二层具有邻近所述第一层设置的第一侧和第二侧; 以及布置成与第二层的第二侧相邻的衬底。布置在基板中的第一阱。第一井与第二层的第二侧相邻。衬底和第一阱具有相反的掺杂。

4. 发明授权

US08901648B2 MOS device with low on-resistance 有权
标题翻译：具有低导通电阻的MOS器件
公开(公告)号：US08901648B2
公开(公告)日：2014-12-02
申请号：US12337059
申请日：2008-12-17
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy
IPC分类号： H01L29/78 , H01L29/423 , H01L29/06 , H01L29/417
CPC分类号： H01L29/78 , H01L29/0692 , H01L29/0696 , H01L29/41725 , H01L29/4238 , H01L29/7816
摘要： Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is situated across from a corresponding side of the drain region, and a plurality of bulk regions arranged around the gate region, wherein one or more of the plurality of source regions separate one or more of the plurality of bulk regions from the gate region. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供一种金属氧化物半导体（MOS）器件，其包括漏极区域，围绕漏极区域并围绕漏极区域形成的环路的栅极区域，围绕栅极区域布置的多个源极区域，其中每个源极区域位于所述漏极区域的对应侧两侧，以及围绕所述栅极区域布置的多个主体区域，其中所述多个源极区域中的一个或多个将所述多个体区域中的一个或多个与所述多个区域门区域。还描述和要求保护其他实施例。

5. 发明授权

US08374004B2 Isolated AC-DC converter with master controller on secondary side and slave controller on primary side 有权
标题翻译：隔离式AC-DC转换器，主控制器在次级侧，从控制器在初级侧
公开(公告)号：US08374004B2
公开(公告)日：2013-02-12
申请号：US12814957
申请日：2010-06-14
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy , Wanfeng Zhang
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy , Wanfeng Zhang
IPC分类号： H02M3/335
CPC分类号： H02M3/335 , H02M3/33538
摘要： An isolated alternating current (AC)-direct current (DC) converter is disclosed. The isolated AC-DC converter comprises a slave control circuit including a slave driver module configured to receive a command and to control coupling of the slave control circuit to a primary-side inductor of a transformer based on the command, a master control circuit coupled to a secondary-side inductor of the transformer, the master control circuit including a master control module configured to sense a feedback voltage across a load and to generate the command based on the feedback voltage and a reference voltage, and a coupler configured to communicate the command from the master control module to the slave driver module and to provide isolation between the master control module and the slave driver module.
摘要翻译：公开了一种隔离交流（AC） - 直流（DC）转换器。隔离式AC-DC转换器包括从控制电路，其包括被配置为接收命令的从驱动器模块，并且基于该命令控制从控制电路与变压器的初级侧电感器的耦合，主控制电路耦合到所述变压器的次级侧电感器，所述主控制电路包括主控制模块，所述主控制模块被配置为感测跨过负载的反馈电压并且基于所述反馈电压和参考电压产生所述指令;以及耦合器，被配置为将所述指令从主控模块到从属驱动模块，并提供主控模块和从驱动模块之间的隔离。

6. 发明授权

US09466596B2 Geometry of MOS device with low on-resistance 有权
标题翻译：具有低导通电阻的MOS器件的几何
公开(公告)号：US09466596B2
公开(公告)日：2016-10-11
申请号：US11964696
申请日：2007-12-26
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy
IPC分类号： H01L29/66 , H01L27/02 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/417
CPC分类号： H01L27/0207 , H01L21/823437 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/41725 , H01L29/41758 , H01L29/4238 , H01L29/78 , H01L29/7835
摘要： A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
摘要翻译：在基板上形成的金属氧化物半导体（MOS）器件和形成MOS器件的方法。 MOS器件包括漏极区域，围绕漏极区域的栅极区域，围绕栅极区域和漏极区域布置的源极区域以及围绕栅极区域布置并分离源极区域的体区域。栅极区域围绕漏极区域形成环路。以这种方式，MOS器件的导通电阻（Ron）减小而不增加MOS器件的面积。

7. 发明申请

US20090250751A1 MOS DEVICE WITH LOW ON-RESISTANCE 有权
标题翻译：具有低电阻性的MOS器件
公开(公告)号：US20090250751A1
公开(公告)日：2009-10-08
申请号：US12337059
申请日：2008-12-17
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/0692 , H01L29/0696 , H01L29/41725 , H01L29/4238 , H01L29/7816
摘要： Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is situated across from a corresponding side of the drain region, and a plurality of bulk regions arranged around the gate region, wherein one or more of the plurality of source regions separate one or more of the plurality of bulk regions from the gate region. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供一种金属氧化物半导体（MOS）器件，其包括漏极区域，围绕漏极区域并围绕漏极区域形成的环路的栅极区域，围绕栅极区域布置的多个源极区域，其中每个源极区域位于所述漏极区域的对应侧两侧，以及围绕所述栅极区域布置的多个主体区域，其中所述多个源极区域中的一个或多个将所述多个体区域中的一个或多个与所述多个区域门区域。还描述和要求保护其他实施例。

8. 发明申请

US20080157195A1 GEOMETRY OF MOS DEVICE WITH LOW ON-RESISTANCE 有权
标题翻译：具有低电阻性的MOS器件的几何
公开(公告)号：US20080157195A1
公开(公告)日：2008-07-03
申请号：US11964696
申请日：2007-12-26
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336
CPC分类号： H01L27/0207 , H01L21/823437 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/41725 , H01L29/41758 , H01L29/4238 , H01L29/78 , H01L29/7835
摘要： A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
摘要翻译：在基板上形成的金属氧化物半导体（MOS）器件和形成MOS器件的方法。 MOS器件包括漏极区域，围绕漏极区域的栅极区域，围绕栅极区域和漏极区域布置的源极区域以及围绕栅极区域布置并分离源极区域的体区域。栅极区域围绕漏极区域形成环路。以这种方式，MOS器件的导通电阻（Ron）减小而不增加MOS器件的面积。

9. 发明申请

US20110038184A1 Isolated AC-DC Converter with Master Controller on Secondary Side and Slave Controller on Primary Side 有权
标题翻译：隔离式AC-DC转换器与主控制器在次级侧和从控制器在一侧
公开(公告)号：US20110038184A1
公开(公告)日：2011-02-17
申请号：US12814957
申请日：2010-06-14
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy , Wanfeng Zhang
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy , Wanfeng Zhang
IPC分类号： H02M3/335
CPC分类号： H02M3/335 , H02M3/33538
摘要： An isolated alternating current (AC)-direct current (DC) converter is disclosed. The isolated AC-DC converter comprises a slave control circuit including a slave driver module configured to receive a command and to control coupling of the slave control circuit to a primary-side inductor of a transformer based on the command, a master control circuit coupled to a secondary-side inductor of the transformer, the master control circuit including a master control module configured to sense a feedback voltage across a load and to generate the command based on the feedback voltage and a reference voltage, and a coupler configured to communicate the command from the master control module to the slave driver module and to provide isolation between the master control module and the slave driver module.
摘要翻译：公开了一种隔离交流（AC） - 直流（DC）转换器。隔离式AC-DC转换器包括从控制电路，其包括被配置为接收命令的从驱动器模块，并且基于该命令控制从控制电路与变压器的初级侧电感器的耦合，主控制电路耦合到所述变压器的次级侧电感器，所述主控制电路包括主控制模块，所述主控制模块被配置为感测跨过负载的反馈电压并且基于所述反馈电压和参考电压产生所述指令;以及耦合器，被配置为将所述指令从主控模块到从属驱动模块，并提供主控模块和从驱动模块之间的隔离。

10. 发明公开

US20240356499A1 ULTRA LINEAR CLASS AB, RF AMPLIFIER TOPOLOGY 审中-公开
公开(公告)号：US20240356499A1
公开(公告)日：2024-10-24
申请号：US18622565
申请日：2024-03-29
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03F1/56 , H03F3/24
CPC分类号： H03F1/565 , H03F3/245 , H03F2200/222 , H03F2200/387 , H03F2200/451
摘要： An amplifier system comprising an input matching network configured to receive an input signal from a signal source. The input matching network is configured to impedance match between the amplifier system and the signal source. An input transformer is configured to receive the impedance matched input signal and perform voltage step down and current step up. An amplifier is configured to receive and amplify an output signal from the input transformer to generate an amplified signal. A low winding ratio output transformer provides isolation between an antenna and amplifier. An output matching network is configured to impedance match to an antenna and provide voltage step up. The input transformer may have a ratio of 2N:N, such as 2:1 ratio. At least one center tap of the input transformer may connect to a bias voltage. The amplifier system may be configured for operation in the radio frequency band.

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