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1. 发明授权

US5911064A Clock multiplexer with selection and deselection of clock modules 失效
标题翻译：时钟复用器，选择和取消选择时钟模块
公开(公告)号：US5911064A
公开(公告)日：1999-06-08
申请号：US988711
申请日：1997-12-11
申请人： Sebastianus M. Samsom , Aloysius P. Thijssen , Keith Baker
发明人： Sebastianus M. Samsom , Aloysius P. Thijssen , Keith Baker
IPC分类号： H03K5/00 , G06F1/06 , H03K17/00
CPC分类号： H03K17/002 , G06F1/04
摘要： A circuit includes a plurality of logically identical clock modules which are all capable of driving the same clock output. The circuit has a selection input for selecting one of the clock modules for driving the clock output. After a change of the selection, a clock module just deselected awaits the completion of a period of the own clock signal before switching to deselection. The clock modules have a hold-off input which is coupled to a common signal line. A newly selected clock module switches to a selection state only after a beginning of a period of the own clock signal, provided that the selected clock module previously detects a signal on its hold-off input which indicates that all clock modules have deselected themselves. The common signal line is preferably coupled to the clock output, deselection being detected on the basis of the signal level which occurs after the beginning of the period after a change of the selection.
摘要翻译：电路包括多个逻辑上相同的时钟模块，它们都能够驱动相同的时钟输出。电路具有用于选择用于驱动时钟输出的时钟模块之一的选择输入。在更改选择之后，刚刚取消选择的时钟模块等待完成自己的时钟信号的一段时间，然后再切换到取消选择。时钟模块具有耦合到公共信号线的保持输入。新选择的时钟模块仅在自己的时钟信号的周期的开始之后切换到选择状态，前提是所选择的时钟模块先前在其保持输入端检测到指示所有时钟模块已被取消选择的信号。公共信号线优选地耦合到时钟输出，基于在选择改变之后的周期开始之后发生的信号电平来检测取消选择。

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