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1. 发明申请

US20110133304A1 Structure and Method for Placement, Sizing and Shaping of Dummy Structures 审中-公开
标题翻译：虚拟结构的放置，尺寸和成形的结构和方法
公开(公告)号：US20110133304A1
公开(公告)日：2011-06-09
申请号：US12980268
申请日：2010-12-28
申请人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
发明人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
IPC分类号： H01L29/00 , H01L21/66
CPC分类号： H01L22/10 , B81C1/00539 , G06F17/5068 , H01L21/027 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/82
摘要： A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.
摘要翻译：芯片包括多个层中的多个功能区域和该层内的多个虚设结构。虚拟结构与功能区域间隔开。每个虚拟结构具有作为功能区域的大小和密度的函数的大小。

2. 发明授权

US07868427B2 Structure and method for placement, sizing and shaping of dummy structures 有权
标题翻译：虚拟结构的放置，尺寸和成形的结构和方法
公开(公告)号：US07868427B2
公开(公告)日：2011-01-11
申请号：US12353193
申请日：2009-01-13
申请人： Sebastian Schmidt , Hang-Yip Liu , Thomas Schafbauer , Yayi Wei
发明人： Sebastian Schmidt , Hang-Yip Liu , Thomas Schafbauer , Yayi Wei
IPC分类号： H01L21/76 , H01L21/4763 , H01L21/302 , H01L23/544
CPC分类号： H01L22/10 , B81C1/00539 , G06F17/5068 , H01L21/027 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/82
摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.
摘要翻译：正在处理的衬底上的材料层，例如，以形成芯片，包括一个或多个功能结构。为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

3. 发明申请

US20090124027A1 Structure and Method for Placement, Sizing and Shaping of Dummy Structures 有权
标题翻译：虚拟结构的放置，尺寸和成形的结构和方法
公开(公告)号：US20090124027A1
公开(公告)日：2009-05-14
申请号：US12353193
申请日：2009-01-13
申请人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
发明人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
IPC分类号： H01L21/66
CPC分类号： H01L22/10 , B81C1/00539 , G06F17/5068 , H01L21/027 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/82
摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.
摘要翻译：正在处理的衬底上的材料层，例如，以形成芯片，包括一个或多个功能结构。为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

4. 发明授权

US07494930B2 Structure and method for placement, sizing and shaping of dummy structures 有权
标题翻译：虚拟结构的放置，尺寸和成形的结构和方法
公开(公告)号：US07494930B2
公开(公告)日：2009-02-24
申请号：US11441649
申请日：2006-05-26
申请人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
发明人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
IPC分类号： H01L21/302
CPC分类号： H01L22/10 , B81C1/00539 , G06F17/5068 , H01L21/027 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/82
摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.
摘要翻译：正在处理的衬底上的材料层，例如，以形成芯片，包括一个或多个功能结构。为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

5. 发明授权

US07071074B2 Structure and method for placement, sizing and shaping of dummy structures 有权
公开(公告)号：US07071074B2
公开(公告)日：2006-07-04
申请号：US10671123
申请日：2003-09-24
申请人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
发明人： Sebastian Schmidt , Thomas Schafbauer , Hang Yip Liu , Yayi Wei
IPC分类号： H01L21/76 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L22/10 , B81C1/00539 , G06F17/5068 , H01L21/027 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/82
摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

6. 发明申请

US20050064634A1 Structure and method for placement, sizing and shaping of dummy structures 有权
标题翻译：虚拟结构的放置，尺寸和成形的结构和方法
公开(公告)号：US20050064634A1
公开(公告)日：2005-03-24
申请号：US10671123
申请日：2003-09-24
申请人： Sebastian Schmidt , Thomas Schafbauer , Hang Liu , Yayi Wei
发明人： Sebastian Schmidt , Thomas Schafbauer , Hang Liu , Yayi Wei
IPC分类号： G06F17/50 , H01L21/027 , H01L21/3105 , H01L21/321 , H01L21/762 , H01L21/82 , H01L21/338 , H01L21/331 , H01L21/8222
CPC分类号： H01L22/10 , B81C1/00539 , G06F17/5068 , H01L21/027 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/82
摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.
摘要翻译：正在处理的衬底上的材料层，例如，以形成芯片，包括一个或多个功能结构。为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

7. 发明申请

US20060216905A1 Structure and method for placement, sizing and shaping of dummy structures 有权
公开(公告)号：US20060216905A1
公开(公告)日：2006-09-28
申请号：US11441649
申请日：2006-05-26
申请人： Sebastian Schmidt , Thomas Schafbauer , Hang Liu , Yayi Wei
发明人： Sebastian Schmidt , Thomas Schafbauer , Hang Liu , Yayi Wei
IPC分类号： H01L21/4763 , H01L21/76 , H01L21/461
CPC分类号： H01L22/10 , B81C1/00539 , G06F17/5068 , H01L21/027 , H01L21/31053 , H01L21/3212 , H01L21/76229 , H01L21/82
摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

8. 发明授权

US08227174B2 Patterning methods and masks 有权
标题翻译：图案化方法和面具
公开(公告)号：US08227174B2
公开(公告)日：2012-07-24
申请号：US12715215
申请日：2010-03-01
申请人： Yayi Wei
发明人： Yayi Wei
IPC分类号： G03F7/26
CPC分类号： G03F1/50 , G03F1/30
摘要： Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.
摘要翻译：公开了用于半导体器件的图案化材料层的掩模，图案化方法和制造半导体器件的方法以及光刻系统。光刻掩模包括交替的线和空间的图案，其中线和间隔包括不同的宽度。当光刻掩模用于对半导体器件的材料层进行图案化时，材料层的图案包括具有基本上相同宽度的交替线和间隔。

9. 发明授权

US07662436B1 Method of spin coating a film of non-uniform thickness 有权
标题翻译：旋涂不均匀薄膜的方法
公开(公告)号：US07662436B1
公开(公告)日：2010-02-16
申请号：US11139122
申请日：2005-05-27
申请人： Yayi Wei , Stefan Brandl
发明人： Yayi Wei , Stefan Brandl
IPC分类号： B05D3/12
CPC分类号： G03F7/162 , B05D1/005
摘要： Embodiments of the invention provide a method for spin coating a film onto a substrate. Preferred embodiments deposit a film, such as a resist, having a thickness gradient from the substrate's centrifugal center to its edge. The gradient may be linear or stepwise continuous, for example. Other embodiments of the invention provide a semiconductor fabrication method. The method comprises forming a resist layer having a predetermined thickness on a substrate. Preferably, the predetermining includes making swing curve measurements on a single test wafer that is coated according to embodiments of the invention.
摘要翻译：本发明的实施方案提供了将膜旋涂到基底上的方法。优选实施例将具有从基板的离心中心到其边缘的厚度梯度的膜例如抗蚀剂沉积。梯度可以是例如线性或逐步连续的。本发明的其他实施例提供半导体制造方法。该方法包括在衬底上形成具有预定厚度的抗蚀剂层。优选地，预先确定包括在根据本发明的实施例涂覆的单个测试晶片上进行摆动曲线测量。

10. 发明申请

US20080070126A1 Patterning masks, methods, and systems 审中-公开
标题翻译：模拟掩模，方法和系统
公开(公告)号：US20080070126A1
公开(公告)日：2008-03-20
申请号：US11523676
申请日：2006-09-19
申请人： Yayi Wei
发明人： Yayi Wei
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/34 , G03F1/26 , G03F1/32 , G03F1/50
摘要： Masks for patterning material layers of semiconductor devices, methods of manufacturing semiconductor devices, and lithography systems are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a lithography mask, the lithography mask including at least one attenuation region. The at least one attenuation region includes an array of sub-resolution features. A workpiece is provided, the workpiece having a layer of photosensitive material disposed thereon. The layer of photosensitive material is affected using the lithography mask.
摘要翻译：公开了用于半导体器件的图案化材料层的掩模，半导体器件的制造方法和光刻系统。在优选实施例中，制造半导体器件的方法包括提供光刻掩模，所述光刻掩模包括至少一个衰减区域。所述至少一个衰减区域包括子分辨率特征的阵列。提供工件，工件具有设置在其上的感光材料层。使用光刻掩模影响感光材料层。

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