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1. 发明申请

US20100038624A1 MEMORY DEVICE HAVING HIGHLY INTEGRATED CELL STRUCTURE AND METHOD OF ITS FABRICATION 审中-公开
标题翻译：具有高度集成的单元结构的存储器件及其制造方法
公开(公告)号：US20100038624A1
公开(公告)日：2010-02-18
申请号：US12603860
申请日：2009-10-22
申请人： Se-Ho Lee , Jae-Hee Oh , Jae-Hyun Park
发明人： Se-Ho Lee , Jae-Hee Oh , Jae-Hyun Park
IPC分类号： H01L45/00
CPC分类号： H01L27/101 , H01L27/24
摘要： In an embodiment, a memory device, with a highly integrated cell structure, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the mold insulating layer. In this case, each of the data storage elements may include a resistor pattern and a barrier pattern, which are sequentially stacked, and the resistor pattern may be self-aligned with the barrier pattern.
摘要翻译：在一个实施例中，具有高度集成的单元结构的存储器件包括设置在半导体衬底上的模具绝缘层。在模具绝缘层上设置至少一根导线。与导线自对准的数据存储元件插入在导线和模绝缘层之间。在这种情况下，每个数据存储元件可以包括顺序堆叠的电阻器图案和阻挡图案，并且电阻器图案可以与屏障图案自对准。

2. 发明授权

US07442602B2 Methods of fabricating phase change memory cells having a cell diode and a bottom electrode self-aligned with each other 有权
标题翻译：制造具有电池二极管和彼此自对准的底部电极的相变存储单元的方法
公开(公告)号：US07442602B2
公开(公告)日：2008-10-28
申请号：US11389996
申请日：2006-03-27
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L21/8234
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.
摘要翻译：在其中提供具有垂直二极管的集成电路器件。这些器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。底部电极与垂直二极管自对准。底部电极的顶表面积小于接触孔的水平截面面积。还提供了形成集成电路器件和相变存储器单元的方法。

3. 发明申请

US20060237756A1 Phase change memory devices and their methods of fabrication 有权
公开(公告)号：US20060237756A1
公开(公告)日：2006-10-26
申请号：US11392310
申请日：2006-03-28
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L29/94
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1666
摘要： In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

4. 发明授权

US07598112B2 Phase change memory devices and their methods of fabrication 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07598112B2
公开(公告)日：2009-10-06
申请号：US11392310
申请日：2006-03-28
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L29/04
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1666
摘要： In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.
摘要翻译：在一个实施例中，相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的第一层间绝缘层。一个孔穿透第一层间绝缘层。第一和第二半导体图案顺序地堆叠在孔的下部区域中。电池电极设置在第二半导体图案上。电池电极具有比第一层间绝缘层的顶表面更低的表面。限制的相变材料图案填充电池电极上的孔。上电极设置在相变材料图案上。孔中的相变材料图案通过孔与第一和第二半导体图案自对准。还提供了一种制造相变存储器件的方法。

5. 发明授权

US07534723B2 Methods of forming fine patterns, and methods of forming trench isolation layers using the same 失效
标题翻译：形成精细图案的方法以及使用其形成沟槽隔离层的方法
公开(公告)号：US07534723B2
公开(公告)日：2009-05-19
申请号：US11519081
申请日：2006-09-11
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L21/76 , H01L21/027 , H01L21/033 , C03C25/68 , C23F1/00 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/3086 , H01L21/3088 , H01L21/76224 , H01L21/76229 , H01L21/76838
摘要： Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.
摘要翻译：形成精细图案的方法包括在基板上形成下层，在下层上形成具有第一间距的初步硬掩模图案，初步硬掩模图案具有第一宽度并且彼此间隔开第二宽度较小比第一宽。使用初步硬掩模图案作为蚀刻掩模蚀刻下层，从而形成初步的底层图案。初步硬掩模图案被拉回，从而在初始底层图案上形成硬掩模图案。在基板上形成覆盖层，暴露硬掩模图案的顶表面。使用覆盖层作为蚀刻掩模蚀刻设置在硬掩模图案之下的硬掩模图案和初始底层图案，由此形成具有小于第一间距的第二间距的下面的图案，并且去除覆盖层。

6. 发明申请

US20070059934A1 Methods of forming fine patterns, and methods of forming trench isolation layers using the same 失效
标题翻译：形成精细图案的方法以及使用其形成沟槽隔离层的方法
公开(公告)号：US20070059934A1
公开(公告)日：2007-03-15
申请号：US11519081
申请日：2006-09-11
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/3086 , H01L21/3088 , H01L21/76224 , H01L21/76229 , H01L21/76838
摘要： Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.
摘要翻译：形成精细图案的方法包括在基板上形成下层，在下层上形成具有第一间距的初步硬掩模图案，初步硬掩模图案具有第一宽度并且彼此间隔开第二宽度较小比第一宽。使用初步硬掩模图案作为蚀刻掩模蚀刻下层，从而形成初步的底层图案。初步硬掩模图案被拉回，从而在初始底层图案上形成硬掩模图案。在基板上形成覆盖层，暴露硬掩模图案的顶表面。使用覆盖层作为蚀刻掩模蚀刻设置在硬掩模图案之下的硬掩模图案和初始底层图案，由此形成具有小于第一间距的第二间距的下面的图案，并且去除覆盖层。

7. 发明授权

US08120005B2 Phase change memory devices and their methods of fabrication 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08120005B2
公开(公告)日：2012-02-21
申请号：US12544104
申请日：2009-08-19
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1666
摘要： In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.
摘要翻译：在一个实施例中，相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的第一层间绝缘层。一个孔穿透第一层间绝缘层。第一和第二半导体图案顺序地堆叠在孔的下部区域中。电池电极设置在第二半导体图案上。电池电极具有比第一层间绝缘层的顶表面更低的表面。限制的相变材料图案填充电池电极上的孔。上电极设置在相变材料图案上。孔中的相变材料图案通过孔与第一和第二半导体图案自对准。还提供了制造相变存储器件的方法。

8. 发明授权

US07671395B2 Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other 失效
标题翻译：具有单元二极管和底部电极彼此自对准的相变存储单元
公开(公告)号：US07671395B2
公开(公告)日：2010-03-02
申请号：US12240267
申请日：2008-09-29
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L27/108
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.
摘要翻译：在其中提供具有垂直二极管的集成电路器件。这些器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。底部电极与垂直二极管自对准。底部电极的顶表面积小于接触孔的水平截面面积。还提供了形成集成电路器件和相变存储器单元的方法。

9. 发明授权

US07625777B2 Memory device having highly integrated cell structure and method of its fabrication 有权
标题翻译：具有高度集成的单元结构的存储器件及其制造方法
公开(公告)号：US07625777B2
公开(公告)日：2009-12-01
申请号：US11428500
申请日：2006-07-03
申请人： Se-Ho Lee , Jae-Hee Oh , Jae-Hyun Park
发明人： Se-Ho Lee , Jae-Hee Oh , Jae-Hyun Park
IPC分类号： H01L21/336
CPC分类号： H01L27/101 , H01L27/24
摘要： In an embodiment, a memory device, with a highly integrated cell stricture, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the mold insulating layer. In this case, each of the data storage elements may include a resistor pattern and a barrier pattern, which are sequentially stacked, and the resistor pattern may be self-aligned with the barrier pattern.
摘要翻译：在一个实施例中，具有高度集成的单元结构的存储器件包括设置在半导体衬底上的模具绝缘层。在模具绝缘层上设置至少一根导线。与导线自对准的数据存储元件插入在导线和模绝缘层之间。在这种情况下，每个数据存储元件可以包括顺序堆叠的电阻器图案和阻挡图案，并且电阻器图案可以与阻挡图案自对准。

10. 发明申请

US20090026439A1 Phase Change Memory Cells Having a Cell Diode and a Bottom Electrode Self-Aligned with Each Other 失效
标题翻译：具有电池二极管和底部电极的相变存储器单元彼此自对准
公开(公告)号：US20090026439A1
公开(公告)日：2009-01-29
申请号：US12240267
申请日：2008-09-29
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.
摘要翻译：在其中提供具有垂直二极管的集成电路器件。这些器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。底部电极与垂直二极管自对准。底部电极的顶表面积小于接触孔的水平截面面积。还提供了形成集成电路器件和相变存储器单元的方法。

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