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1. 发明申请

US20080153179A1 Magnetic random access memory device and method of forming the same 有权
公开(公告)号：US20080153179A1
公开(公告)日：2008-06-26
申请号：US12073098
申请日：2008-02-29
申请人： Se-Chung OH , Jang-Eun LEE , Jun-Soo BAE , Hyun-Jo KIM , Kyung-Tae NAM , Young-Ki HA
发明人： Se-Chung OH , Jang-Eun LEE , Jun-Soo BAE , Hyun-Jo KIM , Kyung-Tae NAM , Young-Ki HA
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , B82Y10/00 , B82Y25/00 , G11B5/3909 , H01L27/228 , H01L43/08 , H01L43/12 , Y10T29/49034 , Y10T29/49044
摘要： Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

2. 发明申请

US20070041243A1 MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US20070041243A1
公开(公告)日：2007-02-22
申请号：US11465075
申请日：2006-08-16
申请人： Jun-Soo BAE , Jang-Eun LEE , Hyun-Jo KIM , Se-Chung OH , Kyung-Tae NAM
发明人： Jun-Soo BAE , Jang-Eun LEE , Hyun-Jo KIM , Se-Chung OH , Kyung-Tae NAM
IPC分类号： G11C11/00
CPC分类号： G11C11/15 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F10/3272 , H01F10/3281 , H01F41/302 , H01L43/08
摘要： There is provided a magnetic memory device and a method of forming the same. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.
摘要翻译：提供了一种磁存储器件及其形成方法。磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。在存储和无引导模式之间插入一个自由的反转模式。自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。

3. 发明申请

US20120327707A1 MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF WRITING DATA THEREIN 有权
标题翻译：磁性随机访问存储器件及其数据写入方法
公开(公告)号：US20120327707A1
公开(公告)日：2012-12-27
申请号：US13532811
申请日：2012-06-26
申请人： Su-Jin AHN , Kyung-Tae NAM
发明人： Su-Jin AHN , Kyung-Tae NAM
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/161
摘要： In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.
摘要翻译：在MRAM装置中写入数据的方法中，在MRAM装置的多个存储单元中选择第一操作单元。第一至第n开关脉冲被顺序地施加到第一操作单元以分别在第一操作单元的第一至第n组存储单元中写入数据。第n开关脉冲的电流电平可以低于第（n-1）个开关脉冲的电流电平，其中n是大于至少1的整数。第n个开关脉冲的脉冲宽度可以窄于的第（n-1）个开关脉冲，其中n是大于至少1的整数。可以对第二操作单元重复该技术。公开了一种装置和系统，其中不同的电流切换脉冲被施加到第一和/或第二操作单元内的多组存储器单元。

4. 发明申请

US20120315707A1 MAGNETIC PATTERNS AND METHODS OF FORMING MAGNETIC PATTERNS 有权
标题翻译：磁性图案和形成磁性图案的方法
公开(公告)号：US20120315707A1
公开(公告)日：2012-12-13
申请号：US13490681
申请日：2012-06-07
申请人： Kyung-Tae NAM
发明人： Kyung-Tae NAM
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228
摘要： In a method of forming a magnetic pattern, a lower electrode layer is formed on a substrate. An insulating interlayer is formed on the lower electrode layer. The insulating interlayer is partially removed to form an opening. A first pinned layer pattern filling the opening is formed. A second pinned layer, a tunnel barrier layer, a free layer and an upper electrode layer are formed on the insulating interlayer and the first pinned layer pattern. The upper electrode layer, the free layer, the tunnel barrier layer and the second pinned layer are patterned to form a second pinned layer pattern, a tunnel barrier pattern, a free layer pattern and an upper electrode. The second pinned layer pattern covers an upper surface of the first pinned layer pattern.
摘要翻译：在形成磁图案的方法中，在基板上形成下电极层。在下电极层上形成绝缘中间层。部分去除绝缘中间层以形成开口。形成填充开口的第一固定层图案。在绝缘中间层和第一被钉扎层图案上形成第二被钉扎层，隧道势垒层，自由层和上部电极层。图案化上电极层，自由层，隧道势垒层和第二被钉扎层，以形成第二固定层图案，隧道势垒图案，自由层图案和上电极。第二钉扎层图案覆盖第一钉扎层图案的上表面。

5. 发明申请

US20160276575A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20160276575A1
公开(公告)日：2016-09-22
申请号：US15170409
申请日：2016-06-01
申请人： Kyung-Tae NAM , Kil-Ho LEE
发明人： Kyung-Tae NAM , Kil-Ho LEE
IPC分类号： H01L43/02 , H01L27/22 , H01L43/12 , H01L43/08 , H01L43/10
CPC分类号： H01L43/02 , G11C11/161 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.

6. 发明申请

US20150188037A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20150188037A1
公开(公告)日：2015-07-02
申请号：US14453110
申请日：2014-08-06
申请人： Kyung-Tae NAM , Kil-Ho LEE
发明人： Kyung-Tae NAM , Kil-Ho LEE
IPC分类号： H01L43/12 , H01L43/08 , H01L27/22 , H01L43/02
CPC分类号： H01L43/02 , G11C11/161 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.
摘要翻译：在制造MRAM器件的方法中，可以形成顺序堆叠在衬底上的下电极，第一钉扎层图案，隧道势垒层图案和自由层图案。可以在基板上形成第一绝缘中间层以覆盖下电极，第一钉扎层图案，隧道势垒层图案和自由层图案。可以蚀刻第一绝缘中间层以形成露出自由层图案的顶表面的凹部。可以形成第二钉扎层图案以填充凹部的至少一部分。可以在第二钉扎层图案上形成布线。

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