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1. 发明授权

US08581383B2 3-D semiconductor die structure with containing feature and method 有权
标题翻译：具有三维半导体芯片结构的特征和方法
公开(公告)号：US08581383B2
公开(公告)日：2013-11-12
申请号：US12877193
申请日：2010-09-08
申请人： Scott K. Pozder , Ritwik Chatterjee
发明人： Scott K. Pozder , Ritwik Chatterjee
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/06102 , H01L2224/10135 , H01L2224/10165 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14517 , H01L2224/16 , H01L2224/16503 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2224/83365 , H01L2224/83385 , H01L2225/06513 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/00014 , H01L2224/13099 , H01L2924/01007
摘要： A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.
摘要翻译：模具上的模具组件具有第一模具（10）和第二模具（50）。第一模具（10）具有延伸第一模具上方的第一高度的第一接触延伸部（28,42）和钉（32,44,45）。第二模具（50）具有连接到第一接触延伸部的第二接触延伸部（68），并且具有延伸在围绕钉的第二模具上方的第二高度的容纳特征（62）。钉子延伸穿过包含的特征。因为钉延伸穿过容纳特征，所以第一和第二管芯之间的横向移动可以使钉与接合特征接触并受约束。因此，钉和容纳特征可用于限制第一和第二管芯之间的运动。

2. 发明授权

US07811932B2 3-D semiconductor die structure with containing feature and method 有权
标题翻译：具有三维半导体芯片结构的特征和方法
公开(公告)号：US07811932B2
公开(公告)日：2010-10-12
申请号：US11966077
申请日：2007-12-28
申请人： Scott K. Pozder , Ritwik Chatterjee
发明人： Scott K. Pozder , Ritwik Chatterjee
IPC分类号： H01L21/44
CPC分类号： H01L24/13 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/06102 , H01L2224/10135 , H01L2224/10165 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14517 , H01L2224/16 , H01L2224/16503 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2224/83365 , H01L2224/83385 , H01L2225/06513 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/00014 , H01L2224/13099 , H01L2924/01007
摘要： A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.
摘要翻译：模具上的模具组件具有第一模具（10）和第二模具（50）。第一模具（10）具有延伸第一模具上方的第一高度的第一接触延伸部（28,42）和钉（32,44,45）。第二模具（50）具有连接到第一接触延伸部的第二接触延伸部（68），并且具有延伸在围绕钉的第二模具上方的第二高度的容纳特征（62）。钉子延伸穿过包含的特征。因为钉延伸穿过容纳特征，所以第一和第二管芯之间的横向移动可以导致钉与接合特征接触并被约束。因此，钉和容纳特征可用于限制第一和第二管芯之间的运动。

3. 发明申请

US20090166888A1 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD 有权
标题翻译：具有特征和方法的3-D半导体结构
公开(公告)号：US20090166888A1
公开(公告)日：2009-07-02
申请号：US11966077
申请日：2007-12-28
申请人： Scott K. Pozder , Ritwik Chatterjee
发明人： Scott K. Pozder , Ritwik Chatterjee
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L24/13 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/06102 , H01L2224/10135 , H01L2224/10165 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14517 , H01L2224/16 , H01L2224/16503 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2224/83365 , H01L2224/83385 , H01L2225/06513 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/00014 , H01L2224/13099 , H01L2924/01007
摘要： A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.
摘要翻译：模具上的模具组件具有第一模具（10）和第二模具（50）。第一模具（10）具有延伸第一模具上方的第一高度的第一接触延伸部（28,42）和钉（32,44,45）。第二模具（50）具有连接到第一接触延伸部的第二接触延伸部（68），并且具有延伸在围绕钉的第二模具上方的第二高度的容纳特征（62）。钉子延伸穿过包含的特征。因为钉延伸穿过容纳特征，所以第一和第二管芯之间的横向移动可以使钉与接合特征接触并受约束。因此，钉和容纳特征可用于限制第一和第二管芯之间的运动。

4. 发明授权

US07622313B2 Fabrication of three dimensional integrated circuit employing multiple die panels 有权
标题翻译：采用多个模板制作三维集成电路
公开(公告)号：US07622313B2
公开(公告)日：2009-11-24
申请号：US11193926
申请日：2005-07-29
申请人： Robert E. Jones , Scott K. Pozder
发明人： Robert E. Jones , Scott K. Pozder
IPC分类号： H01L21/00 , B29C65/00
CPC分类号： H01L21/50 , B32B37/00 , H01L22/20 , Y10T156/10 , Y10T156/1052 , Y10T156/1062
摘要： A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.
摘要翻译：组装电子设备的方法包括测试第一晶片的第一晶片以识别功能第一裸片的位置并将第一晶片分成一组面板，其中面板包括第一裸片的MxN阵列。面板结合到第二晶片的面板部位以形成面板堆叠，其中面板部位在第二晶片中限定第二模具的MxN阵列。面板堆叠被锯成包括结合到第二模具的第一模具的装置。可以将第一晶片划分成面板可以静态或动态地进行（以最大化具有超过特定阈值的产量的面板的数量）。可以执行根据功能性模具图案的面板和面板位置的分层以优先地将面板粘合到同一箱的面板位置。

5. 发明授权

US07553753B2 Method of forming crack arrest features in embedded device build-up package and package thereof 有权
标题翻译：在嵌入式装置积层包装及其包装中形成破裂特征的方法
公开(公告)号：US07553753B2
公开(公告)日：2009-06-30
申请号：US11469158
申请日：2006-08-31
申请人： Jie-Hua Zhao , George R. Leal , Robert J. Wenzel , Scott K. Pozder
发明人： Jie-Hua Zhao , George R. Leal , Robert J. Wenzel , Scott K. Pozder
IPC分类号： H01L21/44
CPC分类号： H01L23/49838 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an embedded device build-up package (10) includes forming a first plurality of features (22) over a packaging substrate (12,16,18), wherein the first plurality of features (22) comprises a first feature and a second feature, forming at least a first crack arrest feature (28) in a first crack arrest available region (26), wherein the first crack arrest available region is between the first feature and the second feature, forming a second plurality of features (32) over the first plurality of features (22) wherein the second plurality of features includes a third feature and a fourth feature, and forming at least a second crack arrest feature (36) in a second crack arrest available region (34), wherein the second crack arrest feature (36) is between the third feature and the fourth feature, and the second crack arrest feature (36) is substantially orthogonal to the first crack arrest feature (28).
摘要翻译：形成嵌入式装置积层包装（10）的方法包括在包装基材（12,16,18）上形成第一多个特征（22），其中第一多个特征（22）包括第一特征和第二特征，在第一裂缝停止可用区域（26）中形成至少第一裂纹阻止特征（28），其中所述第一裂缝停止可用区域在所述第一特征和所述第二特征之间，形成第二多个特征（ 32），其中所述第二多个特征包括第三特征和第四特征，并且在第二裂缝停止可用区域（34）中形成至少第二裂缝停止特征（36），其中，第二裂缝停止特征（36）在第三特征和第四特征之间，并且第二裂缝阻塞特征（36）基本上垂直于第一裂缝停止特征（28）。

6. 发明授权

US07169694B2 Method for forming a bond pad interface 有权
标题翻译：形成接合焊盘界面的方法
公开(公告)号：US07169694B2
公开(公告)日：2007-01-30
申请号：US10910036
申请日：2004-08-03
申请人： Scott K. Pozder , Thomas S. Kobayashi
发明人： Scott K. Pozder , Thomas S. Kobayashi
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/05093 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05558 , H01L2224/05559 , H01L2224/05624 , H01L2224/05655 , H01L2224/05669 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01016 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/00014
摘要： A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134). The support structures (138) provide a mechanical barrier that protects the interface between the capping layer (204) and the bond pad (134). Additional mechanical robustness is achieved when the support structures (138) remain coupled to the unremoved portion of the dielectric layer (136), as forces buffered by the support structures (138) are distributed across the dielectric layer (136) and not concentrated at the bond pad location.
摘要翻译：提出了一种能够在探测或包装操作期间施加的外力抵抗的复合焊盘。复合接合焊盘包括形成在半导体衬底（100）上的非自钝化导电接合焊盘（134）。然后在导电接合焊盘（134）之上形成电介质层（136）。去除电介质层（136）的部分，使得电介质层（136）变得穿孔并且导电接合焊盘（134）的一部分被暴露。电介质层（136）的剩余部分形成覆盖该接合焊盘的支撑结构（138）。然后，形成覆盖接合焊盘结构的自钝化导电覆盖层（204），其中电介质层（136）中的穿孔允许封盖层（204）和下焊接垫（204）的暴露部分之间的电接触 134）。支撑结构（138）提供了保护覆盖层（204）和接合焊盘（134）之间的界面的机械屏障。当支撑结构（138）保持耦合到电介质层（136）的未移动部分时，由支撑结构（138）缓冲的力分布在电介质层（136）上并且不集中在电介质层键盘位置。

7. 发明授权

US06951801B2 Metal reduction in wafer scribe area 有权
标题翻译：晶圆划片区金属还原
公开(公告)号：US06951801B2
公开(公告)日：2005-10-04
申请号：US10351798
申请日：2003-01-27
申请人： Scott K. Pozder , Trent S. Uehling , Lakshmi N. Ramanathan
发明人： Scott K. Pozder , Trent S. Uehling , Lakshmi N. Ramanathan
IPC分类号： H01L20060101 , H01L21/20 , H01L21/301 , H01L21/304 , H01L21/3213 , H01L21/78
CPC分类号： H01L21/78 , H01L21/3043 , H01L21/32134
摘要： A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.
摘要翻译：一种用于从半导体晶片的划线区域去除金属的工艺。去除的金属可以包括划线区域的锯路径中的暴露的金属和划线区域的裂纹停止槽中的金属。在一个实例中，通过湿法蚀刻晶片从刻划区域去除铜。在一个实例中，在去除晶片表面上的暴露的阻挡粘附层之后执行湿蚀刻工艺。锯切路径中的金属的去除可以减少在晶片的模具区域的分割期间在锯片上的金属积累量。

8. 发明授权

US07622309B2 Mechanical integrity evaluation of low-k devices with bump shear 失效
标题翻译：具有碰撞剪切力的低k器件的机械完整性评估
公开(公告)号：US07622309B2
公开(公告)日：2009-11-24
申请号：US11168837
申请日：2005-06-28
申请人： Peng Su , Scott K. Pozder , David G. Wontor , Jie-Hua Zhao
发明人： Peng Su , Scott K. Pozder , David G. Wontor , Jie-Hua Zhao
IPC分类号： H01L21/66
CPC分类号： G01R31/046 , H01L22/12 , H01L22/20 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05084 , H01L2224/05147 , H01L2224/05166 , H01L2224/05541 , H01L2224/05556 , H01L2224/05559 , H01L2224/05572 , H01L2224/0558 , H01L2224/05624 , H01L2224/05647 , H01L2224/05671 , H01L2224/05681 , H01L2224/05684 , H01L2224/13006 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/136 , H01L2224/1403 , H01L2224/14051 , H01L2224/14505 , H01L2224/14515 , H01L2924/00013 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/3512 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00012
摘要： A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). The die test structure (11) may also include a dedicated support structure (41) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (18, 22, 26). After mounting the integrated circuit in a test device, a shear knife (601) is positioned for lateral movement to cause the shear knife to contact the stiff structural component (501). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.
摘要翻译：公开了一种用于评估集成电路中的低k互连叠层的机械完整性的凸块剪切试验，该集成电路包括具有刚性结构部件（501,502）的模具测试结构（11），该结构部件位于导电金属焊盘 103）形成在最后的金属层（104）中。模具测试结构（11）还可以包括在导电金属焊盘下方的专用支撑结构（41），其包括形成在互连层（18,22,26）中的预定图案的金属线。在将集成电路安装在测试装置中之后，剪刀（601）被定位用于横向运动，以使剪切刀与刚性结构部件（501）接触。可以评估由剪切刀的横向运动引起的模具测试结构的任何损坏，以评估互连叠层的机械完整性。

9. 发明授权

US07378339B2 Barrier for use in 3-D integration of circuits 有权
标题翻译：用于电路三维集成的屏障
公开(公告)号：US07378339B2
公开(公告)日：2008-05-27
申请号：US11278042
申请日：2006-03-30
申请人： Scott K. Pozder , Lynne M. Michaelson , Varughese Mathew
发明人： Scott K. Pozder , Lynne M. Michaelson , Varughese Mathew
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76898 , H01L21/76805 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/50 , H01L27/0688 , H01L2224/83191 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/14 , H01L2924/00
摘要： A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.
摘要翻译：一种形成半导体器件的方法包括提供具有着陆焊盘的第一集成电路，并且使用至少一个接合层将第二集成电路附接到第一集成电路。第二集成电路具有电路间迹线，电路间迹线具有电路间迹线开口。该方法还包括形成通过第二集成电路的开口，该开口延伸穿过该电路间开口，在该开口中的该电路间的迹线的暴露部分上形成选择性屏障，该开口通过该至少一个接合层到着陆垫，并用导电填充材料填充开口。选择性阻挡层包括钴或镍中的至少一种，并且导电填充材料电连接电路间迹线和着陆焊盘。

10. 发明授权

US07358616B2 Semiconductor stacked die/wafer configuration and packaging and method thereof 有权
标题翻译：半导体堆叠晶片/晶片配置及其封装及其方法
公开(公告)号：US07358616B2
公开(公告)日：2008-04-15
申请号：US11226025
申请日：2005-09-14
申请人： Syed M. Alam , Robert E. Jones , Scott K. Pozder
发明人： Syed M. Alam , Robert E. Jones , Scott K. Pozder
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541
摘要： A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.
摘要翻译：互易设计对称性允许晶片上的堆叠晶片或晶片使用仅仅几层（例如，金属互连层）变化的相同设计或设计。翻转或旋转一个模具或晶片允许堆叠的模具相对于彼此具有相互的取向，其可用于减小垂直堆叠的模具和/或晶片之间所需的互连。当晶片和/或管芯堆叠时，翻转和/或旋转也可用于改善散热。然后可以包装堆叠的晶片或管芯。

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