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1. 发明授权

US06531728B2 Oxide etching method and structures resulting from same 有权
标题翻译：氧化物蚀刻方法和结果相同
公开(公告)号：US06531728B2
公开(公告)日：2003-03-11
申请号：US09864552
申请日：2001-05-23
申请人： Scott J. DeBoer , Terry L. Gilton , Ceredig Roberts
发明人： Scott J. DeBoer , Terry L. Gilton , Ceredig Roberts
IPC分类号： H01L27108
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76877 , H01L28/40 , H01L28/90
摘要： An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.
摘要翻译：蚀刻方法包括在第一绝缘材料层上在衬底组装表面上提供第一绝缘材料层和第二绝缘材料层。当暴露于蚀刻组合物时，第一绝缘材料层具有大于第二绝缘材料层的蚀刻速率的蚀刻速率。至少使用蚀刻组合物去除第一绝缘材料层和第二绝缘材料层的部分。使用该方法形成各种类型的结构（例如，触点，电容器）。

2. 发明授权

US06258729B1 Oxide etching method and structures resulting from same 有权
公开(公告)号：US06258729B1
公开(公告)日：2001-07-10
申请号：US09388685
申请日：1999-09-02
申请人： Scott J. DeBoer , Terry L. Gilton , Ceredig Roberts
发明人： Scott J. DeBoer , Terry L. Gilton , Ceredig Roberts
IPC分类号： H01L21461
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76877 , H01L28/40 , H01L28/90
摘要： An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.

3. 发明授权

US06914017B1 Residue free overlay target 有权
标题翻译：残留免费覆盖目标
公开(公告)号：US06914017B1
公开(公告)日：2005-07-05
申请号：US09651790
申请日：2000-08-30
申请人： Pary Baluswamy , Scott J. DeBoer , Ceredig Roberts , Tim H. Bossart
发明人： Pary Baluswamy , Scott J. DeBoer , Ceredig Roberts , Tim H. Bossart
IPC分类号： G03F7/20 , H01L21/302
CPC分类号： G03F7/70633 , H01L22/34 , Y10S438/975
摘要： The present invention includes a residue-free overlay target, as well as a method of forming a residue-residue free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers, and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.
摘要翻译：本发明包括无残留覆盖靶，以及形成无残留覆盖靶的方法。本发明的无残留覆盖靶由包括一系列凸起线的沟槽或焊盘限定。包括在本发明的覆盖靶中的突起线基本上消除了覆盖材料层的顶表面处的任何表面形貌，例如凹陷，并且因此防止可能掩盖覆盖靶并阻止进一步加工的工艺残留物的堆积。可以使用半导体制造领域中已知的工艺技术来实现和修改本发明的方法，并且包括提供半导体衬底，沉积抗蚀剂层，图案化抗蚀剂，以及执行湿法或干蚀刻以产生至少一个覆盖靶根据本发明。

4. 发明授权

US06822342B2 Raised-lines overlay semiconductor targets and method of making the same 失效
标题翻译：引线覆盖半导体目标及其制作方法
公开(公告)号：US06822342B2
公开(公告)日：2004-11-23
申请号：US09996337
申请日：2001-11-28
申请人： Pary Baluswamy , Scott J. DeBoer , Ceredig Roberts , Tim H. Bossart
发明人： Pary Baluswamy , Scott J. DeBoer , Ceredig Roberts , Tim H. Bossart
IPC分类号： H01L23544
CPC分类号： G03F7/70633 , H01L22/34 , Y10S438/975
摘要： The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.
摘要翻译：本发明包括无残留覆盖靶，以及形成无残留覆盖靶的方法。本发明的无残留覆盖靶由包括一系列凸起线的沟槽或焊盘限定。包括在本发明的覆盖目标物中的凸起线实质上消除了在覆盖材料层的顶表面上的任何表面形貌，例如凹陷，并且因此防止可能掩盖覆盖目标并阻止进一步处理的工艺残余物的累积。可以使用半导体制造领域中已知的工艺技术来实现和修改本发明的方法，并且包括提供半导体衬底，沉积抗蚀剂层，图案化抗蚀剂，以及执行湿法或干蚀刻以产生至少一个覆盖靶根据本发明。

5. 发明授权

US08716116B2 Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline 有权
标题翻译：使用垂直集成的凹槽接入设备和数字线形成DRAM阵列的方法
公开(公告)号：US08716116B2
公开(公告)日：2014-05-06
申请号：US12721373
申请日：2010-03-10
申请人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
发明人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L27/108 , H01L27/10882 , H01L27/10885
摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
摘要翻译：公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

6. 发明申请

US20070045712A1 Memory cell layout and process flow 有权
标题翻译：存储单元格布局和流程
公开(公告)号：US20070045712A1
公开(公告)日：2007-03-01
申请号：US11219349
申请日：2005-09-01
申请人： Gordon Haller , David Hwang , Sanh Tang , Ceredig Roberts
发明人： Gordon Haller , David Hwang , Sanh Tang , Ceredig Roberts
IPC分类号： H01L29/788
CPC分类号： H01L21/3088 , H01L21/0338 , H01L27/0207 , H01L27/10891 , H01L27/10894
摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5 F, while the digit line pitch is about 3 F.
摘要翻译：存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。字线间距约为1.5 F，而数字线间距约为3 F。

7. 发明授权

US5909630A Dual-masked isolation 失效
标题翻译：双屏蔽隔离
公开(公告)号：US5909630A
公开(公告)日：1999-06-01
申请号：US86377
申请日：1998-05-28
申请人： Ceredig Roberts , Werner Juengling
发明人： Ceredig Roberts , Werner Juengling
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/32 , H01L21/76221
摘要： A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.
摘要翻译：场隔离过程利用两个或更多个隔离形成步骤在半导体衬底上形成有源区。每个场隔离步骤以减少场氧化物侵蚀的方式形成场隔离的一部分，特别是通过形成场氧化物岛。现场隔离配置的叠加定义了所需的有效区域。目前优选的双掩模方法可以使用单个掩蔽叠层进行，或者更优选地使用用于每个隔离掩模的掩蔽堆叠。本隔离过程进一步允许针对同一集成电路上的各种隔离要求进行优化的隔离特性。

8. 发明授权

US5861344A Facet etch for improved step coverage of integrated circuit contacts 失效
公开(公告)号：US5861344A
公开(公告)日：1999-01-19
申请号：US958655
申请日：1997-10-27
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

9. 发明授权

US5730835A Facet etch for improved step coverage of integrated circuit contacts 失效
公开(公告)号：US5730835A
公开(公告)日：1998-03-24
申请号：US594842
申请日：1996-01-31
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00 , C23F1/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

10. 发明授权

US5699292A SRAM cell employing substantially vertically elongated pull-up resistors 失效
标题翻译：采用基本垂直细长的上拉电阻的SRAM单元
公开(公告)号：US5699292A
公开(公告)日：1997-12-16
申请号：US705589
申请日：1996-08-29
申请人： Ceredig Roberts
发明人： Ceredig Roberts
IPC分类号： H01L27/11 , H01L27/02
CPC分类号： H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： An SRAM cell having at least four field effect transistors includes, a) at least four transistor gates, a ground line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and b) the Vcc line and the ground line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates. In an additional aspect, an SRAM cell having at least four field effect transistors includes, i) at least four transistor gates, an electrical interconnect line, a Vcc line, and a pair of pull-up resistors; the four transistor gates having associated transistor diffusion regions operatively adjacent thereto; and ii) the Vcc line and the electrical interconnect line being provided in different respective elevational planes, the pull-up resistors being substantially vertically elongated between Vcc and selected of the respective transistor diffusion regions operatively adjacent the gates.
摘要翻译：具有至少四个场效应晶体管的SRAM单元包括：a）至少四个晶体管栅极，接地线，Vcc线和一对上拉电阻; 四个晶体管栅极具有可操作地与其相邻的晶体管扩散区域; 以及b）Vcc线和接地线设置在不同的各个正面中，所述上拉电阻在Vcc之间基本上垂直延伸，并且与所述栅极可操作地相邻的各个晶体管扩散区域选择。在另一方面，具有至少四个场效应晶体管的SRAM单元包括：i）至少四个晶体管栅极，电互连线，Vcc线和一对上拉电阻; 四个晶体管栅极具有可操作地与其相邻的晶体管扩散区域; 以及ii）Vcc线和电互连线设置在不同的各个正面中，所述上拉电阻在Vcc之间基本上垂直延伸，并且与所述栅极可操作地相邻的各个晶体管扩散区域选择。

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