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1. 发明授权

US08677297B2 Low-overhead multi-patterning design rule check 有权
标题翻译：低开销多图案设计规则检查
公开(公告)号：US08677297B2
公开(公告)日：2014-03-18
申请号：US13675970
申请日：2012-11-13
申请人： Scott I. Chase , Zuo Dai , Dick Liu , Ming Su
发明人： Scott I. Chase , Zuo Dai , Dick Liu , Ming Su
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.
摘要翻译：大体上描述的是，系统能够对用户进行多图案化布局违规的快速准确描绘，从而可以手动和实时地校正，并且不会干扰正常的手动编辑过程。在一个实施例中，系统涉及迭代地构建具有识别岛和圆弧的树结构，其识别连接的岛之间的多图案化间隔违例。系统使用先前插入的关系来检测在构建这些树结构期间的着色违规。着色违规优选以候选间隔违规中的周期的视觉指示的形式报告给用户，候选间隔违反也本身以视觉和个别方式指示。用户可以直观地看到如何移动岛周围，以及在哪个方向和距离上移动多个图案间隔违规，从而破坏周期。

2. 发明申请

US20130074024A1 LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECK 有权
标题翻译： LOW-OVERHEAD多图案设计规则检查
公开(公告)号：US20130074024A1
公开(公告)日：2013-03-21
申请号：US13675970
申请日：2012-11-13
申请人： Scott I. Chase , Zuo Dai , Dick Liu , Ming Su
发明人： Scott I. Chase , Zuo Dai , Dick Liu , Ming Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.
摘要翻译：大体上描述的是，系统能够对用户进行多图案化布局违规的快速准确描绘，从而可以手动和实时地校正，并且不会干扰正常的手动编辑过程。在一个实施例中，系统涉及迭代地构建具有识别岛和圆弧的树结构，其识别连接的岛之间的多图案化间隔违例。系统使用先前插入的关系来检测在构建这些树结构期间的着色违规。着色违规优选以候选间隔违规中的周期的视觉指示的形式报告给用户，候选间隔违反也本身以视觉和个别方式指示。用户可以直观地看到如何移动岛周围，以及哪些方向和距离，以便消除多图案化间隔违规，从而破坏周期。

3. 发明申请

US20110016094A1 TRANSACTION HISTORY WITH BOUNDED OPERATION SEQUENCES 有权
标题翻译：具有边界操作序列的交易历史
公开(公告)号：US20110016094A1
公开(公告)日：2011-01-20
申请号：US12610180
申请日：2009-10-30
申请人： Scott I. Chase , Jeffrey T. Brubaker
发明人： Scott I. Chase , Jeffrey T. Brubaker
IPC分类号： G06F17/30 , G06F3/048
CPC分类号： G06F17/5045
摘要： A technique for maintaining a transaction history is described. This transaction history includes a sequence of commands or operations in an electronic-design-automation (EDA) environment. For subsets of one or more operations in the sequence of operations, the transaction history includes an associated transaction name, as well as a state of the of the subset, which is open after an initial EDA operation in the subset has been performed and is closed after a last EDA operation in the subset has been performed. This transaction history can be displayed in a window in a graphical user interface, and facilitates undoing and/or rolling back of changes to the data associated with one or more subsets. For example, if an error is detected, roll back of one or more subsets to a known software state or condition prior to the operations in the one or more subsets may be performed without user instructions using the transaction history.
摘要翻译：描述了一种维护交易历史的技术。该交易历史包括电子设计自动化（EDA）环境中的一系列命令或操作。对于操作序列中的一个或多个操作的子集，事务历史包括关联的事务名称以及该子集的状态，该子集在该子集中的初始EDA操作已被执行并且被关闭之后被打开在子集中的最后EDA操作已经被执行之后。该事务历史可以在图形用户界面的窗口中显示，并且有助于撤销和/或回滚与一个或多个子集相关联的数据的改变。例如，如果检测到错误，则可以在不使用交易历史的用户指令的情况下执行在一个或多个子集中的操作之前将一个或多个子集回滚到已知软件状态或条件。

4. 发明授权

US08706699B2 Transaction history with bounded operation sequences 有权
标题翻译：具有有界运算序列的交易历史
公开(公告)号：US08706699B2
公开(公告)日：2014-04-22
申请号：US12610180
申请日：2009-10-30
申请人： Scott I. Chase , Jeffrey T. Brubaker
发明人： Scott I. Chase , Jeffrey T. Brubaker
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F17/5045
摘要： A technique for maintaining a transaction history is described. This transaction history includes a sequence of commands or operations in an electronic-design-automation (EDA) environment. For subsets of one or more operations in the sequence of operations, the transaction history includes an associated transaction name, as well as a state of the of the subset, which is open after an initial EDA operation in the subset has been performed and is closed after a last EDA operation in the subset has been performed. This transaction history can be displayed in a window in a graphical user interface, and facilitates undoing and/or rolling back of changes to the data associated with one or more subsets. For example, if an error is detected, roll back of one or more subsets to a known software state or condition prior to the operations in the one or more subsets may be performed without user instructions using the transaction history.
摘要翻译：描述了一种维护交易历史的技术。该交易历史包括电子设计自动化（EDA）环境中的一系列命令或操作。对于操作序列中的一个或多个操作的子集，事务历史包括关联的事务名称以及该子集的状态，该子集在该子集中的初始EDA操作已被执行并且被关闭之后被打开在子集中的最后EDA操作已经被执行之后。该事务历史可以在图形用户界面的窗口中显示，并且有助于撤销和/或回滚与一个或多个子集相关联的数据的改变。例如，如果检测到错误，则可以在不使用交易历史的用户指令的情况下执行在一个或多个子集中的操作之前将一个或多个子集回滚到已知软件状态或条件。

5. 发明授权

US08312410B2 Parameterized cell caching in electronic design automation 有权
标题翻译：电子设计自动化中的参数化单元格缓存
公开(公告)号：US08312410B2
公开(公告)日：2012-11-13
申请号：US12718850
申请日：2010-03-05
申请人： William K. Foster , Scott I. Chase
发明人： William K. Foster , Scott I. Chase
IPC分类号： G06F17/50 , G06F11/22 , G06F15/04
CPC分类号： G06F17/50
摘要： Some embodiments provide a system that improves performance during parameterized cell instantiation in an electronic design automation (EDA) application. During operation, the system persists evaluation results associated with a parameterized cell in the design within a session of the EDA application so that the evaluation results are available even after they have been flushed from memory. Further, the system can persist the evaluation results across sessions of the EDA application. Next, the system uses the persisted evaluation results to instantiate the parameterized cell without re-evaluating the parameterized cell. Finally, the system discards the persisted evaluation results based at least on a dependency associated with the parameterized cell.
摘要翻译：一些实施例提供了一种在电子设计自动化（EDA）应用中改善参数化小区实例化期间的性能的系统。在操作期间，系统在EDA应用程序的会话期间，与设计中的参数化单元相关联的评估结果保持不变，以便评估结果即使在从内存中刷新之后也可以使用。此外，该系统可以持续EDA应用程序的评估结果。接下来，系统使用持久化的评估结果来实例化参数化的单元格，而不重新评估参数化的单元格。最后，系统至少基于与参数化单元相关联的依赖关系来舍弃持久的评估结果。

6. 发明授权

US09195791B2 Custom module generation 有权
标题翻译：自定义模块生成
公开(公告)号：US09195791B2
公开(公告)日：2015-11-24
申请号：US12791759
申请日：2010-06-01
申请人： Haichun Chen , Greg Woolhiser , Scott I. Chase
发明人： Haichun Chen , Greg Woolhiser , Scott I. Chase
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： G06F17/5068 , H01L27/0207
摘要： Some embodiments of the present invention create a layout for a circuit design which includes one or more circuit modules. The system can receive a nominal implementation of a circuit module, and a user-defined module generator capable of generating one or more custom implementations of the circuit module from an existing implementation of the circuit module. Next, the system can create the layout for the circuit design by executing the user-defined module generator on at least one processor to generate one or more custom implementations of the circuit module from the nominal implementation. The system can then use the one or more custom implementations of the circuit module in the layout.
摘要翻译：本发明的一些实施例为包括一个或多个电路模块的电路设计创建布局。该系统可以接收电路模块的标称实现，以及能够从电路模块的现有实现中产生电路模块的一个或多个定制实现的用户定义的模块发生器。接下来，系统可以通过在至少一个处理器上执行用户定义的模块发生器来从标称实现生成电路模块的一个或多个定制实现来创建用于电路设计的布局。然后，系统可以在布局中使用电路模块的一个或多个定制实现。

7. 发明申请

US20110296364A1 METHOD AND APPARATUS FOR CUSTOM MODULE GENERATION 有权
标题翻译：自定义模块生成的方法和装置
公开(公告)号：US20110296364A1
公开(公告)日：2011-12-01
申请号：US12791759
申请日：2010-06-01
申请人： Haichun Chen , Greg Woolhiser , Scott I. Chase
发明人： Haichun Chen , Greg Woolhiser , Scott I. Chase
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： Some embodiments of the present invention create a layout for a circuit design which includes one or more circuit modules. The system can receive a nominal implementation of a circuit module, and a user-defined module generator capable of generating one or more custom implementations of the circuit module from an existing implementation of the circuit module. Next, the system can create the layout for the circuit design by executing the user-defined module generator on at least one processor to generate one or more custom implementations of the circuit module from the nominal implementation. The system can then use the one or more custom implementations of the circuit module in the layout.
摘要翻译：本发明的一些实施例为包括一个或多个电路模块的电路设计创建布局。该系统可以接收电路模块的标称实现，以及能够从电路模块的现有实现中产生电路模块的一个或多个定制实现的用户定义的模块发生器。接下来，系统可以通过在至少一个处理器上执行用户定义的模块发生器来从标称实现生成电路模块的一个或多个定制实现来创建用于电路设计的布局。然后，系统可以在布局中使用电路模块的一个或多个定制实现。

8. 发明申请

US20110219349A1 PARAMETERIZED CELL CACHING IN ELECTRONIC DESIGN AUTOMATION 有权
标题翻译：电子设计自动化中的参数化电池高速缓存
公开(公告)号：US20110219349A1
公开(公告)日：2011-09-08
申请号：US12718850
申请日：2010-03-05
申请人： William K. Foster , Scott I. Chase
发明人： William K. Foster , Scott I. Chase
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Some embodiments provide a system that improves performance during parameterized cell instantiation in an electronic design automation (EDA) application. During operation, the system persists evaluation results associated with a parameterized cell in the design within a session of the EDA application so that the evaluation results are available even after they have been flushed from memory. Further, the system can persist the evaluation results across sessions of the EDA application. Next, the system uses the persisted evaluation results to instantiate the parameterized cell without re-evaluating the parameterized cell. Finally, the system discards the persisted evaluation results based at least on a dependency associated with the parameterized cell.
摘要翻译：一些实施例提供了一种在电子设计自动化（EDA）应用中改善参数化小区实例化期间的性能的系统。在操作期间，系统在EDA应用程序的会话期间，与设计中的参数化单元相关联的评估结果保持不变，以便评估结果即使在从内存中刷新之后也可以使用。此外，该系统可以持续EDA应用程序的评估结果。接下来，系统使用持久化的评估结果来实例化参数化的单元格，而不重新评估参数化的单元格。最后，系统至少基于与参数化单元相关联的依赖关系来舍弃持久的评估结果。

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