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1. 发明授权

US07189615B2 Single mask MIM capacitor and resistor with in trench copper drift barrier 有权
标题翻译：单掩模MIM电容器和电阻器具有沟槽铜漂移屏障
公开(公告)号：US07189615B2
公开(公告)日：2007-03-13
申请号：US11037530
申请日：2005-01-18
申请人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
发明人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76816 , H01L21/76849 , H01L23/5223 , H01L28/20 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
摘要翻译：公开了MIM（金属绝缘金属）电容器（164）的形成和电阻器（166）的同时形成。在用作电容器（164）的底部电极（170）的铜沉积（110）上形成铜扩散阻挡层（124）。铜扩散阻挡层（124）减轻了铜从铜沉积物（110）的不期望的扩散，并且通过无电沉积形成，使得在除了顶部表面（125）之外的位置处几乎不会沉积阻挡材料，的铜/底电极的沉积。随后，分别施加介电层（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶电极（174），其中导电顶电极材料层（152）还用于同时开发与电容器（164）相同的芯片上的电阻器（166）。

2. 发明申请

US20060160299A1 Single mask MIM capacitor and resistor with in trench copper drift barrier 有权
标题翻译：单掩模MIM电容器和电阻器具有沟槽铜漂移屏障
公开(公告)号：US20060160299A1
公开(公告)日：2006-07-20
申请号：US11037530
申请日：2005-01-18
申请人： Satyavolu Rao , Darius Crenshaw , Stephan Grunow , Kenneth Brennan , Somit Joshi , Montray Leavy , Phillip Matz , Sameer Ajmera , Yuri Solomentsev
发明人： Satyavolu Rao , Darius Crenshaw , Stephan Grunow , Kenneth Brennan , Somit Joshi , Montray Leavy , Phillip Matz , Sameer Ajmera , Yuri Solomentsev
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76816 , H01L21/76849 , H01L23/5223 , H01L28/20 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
摘要翻译：公开了MIM（金属绝缘金属）电容器（164）的形成和电阻器（166）的同时形成。在用作电容器（164）的底部电极（170）的铜沉积（110）上形成铜扩散阻挡层（124）。铜扩散阻挡层（124）减轻了铜从铜沉积物（110）的不期望的扩散，并且通过无电沉积形成，使得在除了顶部表面（125）之外的位置处几乎不会沉积阻挡材料，的铜/底电极的沉积。随后，分别施加介电层（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶电极（174），其中导电顶电极材料层（152）还用于同时开发与电容器（164）相同的芯片上的电阻器（166）。

3. 发明申请

US20060024962A1 Partial plate anneal plate process for deposition of conductive fill material 有权
标题翻译：导电填充材料沉积的局部板退火板工艺
公开(公告)号：US20060024962A1
公开(公告)日：2006-02-02
申请号：US10901857
申请日：2004-07-28
申请人： Montray Leavy , Stephan Grunow , Satyavolu Papa Rao , Noel Russell
发明人： Montray Leavy , Stephan Grunow , Satyavolu Papa Rao , Noel Russell
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76883
摘要： A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).
摘要翻译：提供一种制造半导体器件的方法。在一个或多个半导体层（402）上形成层间电介质层。在层间电介质层（404）中形成一个或多个特征区域。第一导电层形成在特征区域的至少一部分和层间电介质层（406）上）。执行促进第一导电层（408）的晶粒生长的第一退火。在第一导电层（410）上形成另外的导电层，并执行另外的退火（412），其促进附加导电层的晶粒生长，并进一步促进第一导电层的晶粒尺寸生长。可以形成和退火附加的导电层，直到获得足够的覆盖层数量。随后，进行平面化处理，其去除过量的导电材料，从而形成和隔离半导体器件（414）中的导电特征。

4. 发明授权

US07256121B2 Contact resistance reduction by new barrier stack process 有权
标题翻译：通过新的阻挡层叠工艺降低接触电阻
公开(公告)号：US07256121B2
公开(公告)日：2007-08-14
申请号：US11002935
申请日：2004-12-02
申请人： Duofeng Yue , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell , Montray Leavy
发明人： Duofeng Yue , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell , Montray Leavy
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865
摘要： The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
摘要翻译：本发明提供了一种在半导体衬底100上形成互连的方法。该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。蚀刻还去除了开口130底部的阻挡层230的至少一部分。

5. 发明授权

US07148140B2 Partial plate anneal plate process for deposition of conductive fill material 有权
公开(公告)号：US07148140B2
公开(公告)日：2006-12-12
申请号：US10901857
申请日：2004-07-28
申请人： Montray Leavy , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell
发明人： Montray Leavy , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell
IPC分类号： H10L21/44
CPC分类号： H01L21/76877 , H01L21/76883
摘要： A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).

6. 发明申请

US20060121724A1 Contact resistance reduction by new barrier stack process 有权
标题翻译：通过新的阻挡层叠工艺降低接触电阻
公开(公告)号：US20060121724A1
公开(公告)日：2006-06-08
申请号：US11002935
申请日：2004-12-02
申请人： Duofeng Yue , Stephan Grunow , Satyavolu Papa Rao , Noel Russell , Montray Leavy
发明人： Duofeng Yue , Stephan Grunow , Satyavolu Papa Rao , Noel Russell , Montray Leavy
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865
摘要： The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
摘要翻译：本发明提供了一种在半导体衬底100上形成互连的方法。该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。蚀刻还去除了开口130底部的阻挡物230层的至少一部分。

7. 发明申请

US20110100826A1 SUPERFILLING SECONDARY METALLIZATION PROCESS IN MEMS FABRICATION 有权
标题翻译： MEMS制造中的超级二次金属化过程
公开(公告)号：US20110100826A1
公开(公告)日：2011-05-05
申请号：US12608857
申请日：2009-10-29
申请人： Montray Leavy
发明人： Montray Leavy
IPC分类号： C25D5/16 , B44C1/22 , B32B15/01
CPC分类号： C25D1/003 , B32B15/01 , C25D3/38
摘要： Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and a sacrificial secondary metal that provides structural support for the primary metal component during machining More specifically, techniques are disclosed to increase the rate of secondary metal deposition between primary metal features in order to prevent voiding in the sacrificial secondary metal and thus enhance structural support of the primary metal during machining.
摘要翻译：本文提供了用于利用集成到最终MEMS结构中的主要金属和在加工期间为主要金属部件提供结构支撑的牺牲二次金属制造MEMS的工艺。具体而言，公开了增加次级金属沉积在主金属特征之间以防止牺牲二次金属中的空隙，从而增强在加工过程中初级金属的结构支撑。

8. 发明授权

US08747642B2 Superfilling secondary metallization process in MEMS fabrication 有权
标题翻译：在MEMS制造中超补充二次金属化工艺
公开(公告)号：US08747642B2
公开(公告)日：2014-06-10
申请号：US12608857
申请日：2009-10-29
申请人： Montray Leavy
发明人： Montray Leavy
IPC分类号： C25D5/48
CPC分类号： C25D1/003 , B32B15/01 , C25D3/38
摘要： Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and a sacrificial secondary metal that provides structural support for the primary metal component during machining. More specifically, techniques are disclosed to increase the rate of secondary metal deposition between primary metal features in order to prevent voiding in the sacrificial secondary metal and thus enhance structural support of the primary metal during machining.
摘要翻译：本文提供了用于利用集成到最终MEMS结构中的主金属和在加工期间为主要金属部件提供结构支撑的牺牲二次金属来制造MEMS的工艺。更具体地，公开了用于增加主金属特征之间的二次金属沉积速率的技术，以便防止牺牲二次金属中的空隙，从而增强在加工期间主金属的结构支撑。

9. 发明申请

US20110100829A1 MULTI MATERIAL SECONDARY METALLIZATION SCHEME IN MEMS FABRICATION 有权
标题翻译： MEMS制造中的多材料二次金属化方案
公开(公告)号：US20110100829A1
公开(公告)日：2011-05-05
申请号：US12608873
申请日：2009-10-29
申请人： Montray Leavy
发明人： Montray Leavy
IPC分类号： B32B15/01 , B44C1/22 , C23C28/02
CPC分类号： C23C28/02 , B32B15/01 , Y10T428/12229
摘要： Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primary metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining.
摘要翻译：本文提供了用于利用集成到最终MEMS结构中的主金属和在加工期间为主金属部件提供结构支撑的两个或更多个牺牲二次金属来制造MEMS的工艺。在不使用光刻的情况下，第一二次金属在基底金属周围和基板的整个表面上薄电镀。然后将第二二次金属在不使用光刻的情况下在沉积的第一二次金属上进行厚电镀。此外，公开了增加第一二次金属在主金属特征之间的沉积速率以防止空隙并因此增强在加工期间主金属的结构支撑的技术。

10. 发明申请

US20120070980A1 MULTI MATERIAL SECONDARY METALLIZATION SCHEME IN MEMS FABRICATION 有权
标题翻译： MEMS制造中的多材料二次金属化方案
公开(公告)号：US20120070980A1
公开(公告)日：2012-03-22
申请号：US13308545
申请日：2011-12-01
申请人： Montray Leavy
发明人： Montray Leavy
IPC分类号： H01L21/768
CPC分类号： C23C28/02 , B32B15/01 , Y10T428/12229
摘要： Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primary metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining.
摘要翻译：本文提供了用于利用集成到最终MEMS结构中的主金属和在加工期间为主金属部件提供结构支撑的两个或更多个牺牲二次金属来制造MEMS的工艺。在不使用光刻的情况下，第一二次金属在基底金属周围和基板的整个表面上薄电镀。然后将第二二次金属在不使用光刻的情况下在沉积的第一二次金属上进行厚电镀。此外，公开了增加第一二次金属在主金属特征之间的沉积速率以防止空隙并因此增强在加工期间主金属的结构支撑的技术。

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