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1. 发明授权

US5073117A Flip-chip test socket adaptor and method 失效
标题翻译：倒装芯片测试插座适配器和方法
公开(公告)号：US5073117A
公开(公告)日：1991-12-17
申请号：US620221
申请日：1990-12-27
申请人： Satwinder Malhi , Oh K. Kwon , Shivaling S. Mahant-Shetti
发明人： Satwinder Malhi , Oh K. Kwon , Shivaling S. Mahant-Shetti
IPC分类号： G01R1/04 , H05K7/10
CPC分类号： H05K7/1061 , G01R1/0483 , G01R1/06727 , Y10S439/912 , Y10T29/49004 , Y10T29/4913
摘要： A test set socket adaptor (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adaptor (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate for variations in solder bumps (26) on the bare chip (22). The deflection of the cantilever beams (32) allows a positive contact between the solder bumps (26) and the cantilever beams for an AC and a burn-in test.
摘要翻译：测试套筒适配器（20）包括基板（28），多个悬臂梁（32）和封装件（30）。可以将裸芯片（22）插入并由测试插座适配器（20）保持，以插入到标准测试插座中。悬臂（32）被设计成偏转和补偿裸芯片（22）上的焊料凸块（26）的变化。悬臂梁（32）的偏转允许焊料凸块（26）和悬臂梁之间的正接触用于交流和老化测试。

2. 发明授权

US5006792A Flip-chip test socket adaptor and method 失效
标题翻译：倒装芯片测试插座适配器和方法
公开(公告)号：US5006792A
公开(公告)日：1991-04-09
申请号：US330839
申请日：1989-03-30
申请人： Satwinder Malhi , Oh K. Kwon , Shivaling S. Mahant-Shetti
发明人： Satwinder Malhi , Oh K. Kwon , Shivaling S. Mahant-Shetti
IPC分类号： G01R31/26 , G01R1/04 , H01L21/66 , H05K7/10
CPC分类号： H05K7/1061 , G01R1/0483 , G01R1/06727
摘要： A test set socket adapter (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adapter (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate for variations in solder bumps (26) on the bare chip (22). The deflection of the cantilever beams (32) allows a positive contact between the solder bumps (26) and the cantilever beams for an AC and a burn-in test.
摘要翻译：测试套筒适配器（20）包括基板（28），多个悬臂梁（32）和封装件（30）。可以将裸芯片（22）插入并由测试插座适配器（20）保持，以插入到标准测试插座中。悬臂（32）被设计成偏转和补偿裸芯片（22）上的焊料凸块（26）的变化。悬臂梁（32）的偏转允许焊料凸块（26）和悬臂梁之间的正接触用于交流和老化测试。

3. 发明授权

US06226664B1 Method and device for adding and subtracting thermometer coded data 失效
标题翻译：加减温度计编码数据的方法和装置
公开(公告)号：US06226664B1
公开(公告)日：2001-05-01
申请号：US08277386
申请日：1994-07-19
申请人： Fuk Ho P. Ng , Shivaling S. Mahant-Shetti
发明人： Fuk Ho P. Ng , Shivaling S. Mahant-Shetti
IPC分类号： G06F750
CPC分类号： G06F7/50 , G06F7/544 , G06F2207/5442
摘要： Two thermometer coded words having a most significant byte (MSB) and a least significant byte (LSB) are subtracted, and a check detects a borrowing condition. A first borrowing condition is detected if word B MSB is greater than word A MSB (12), and word A LSB is greater than word B LSB (14). In such a case a borrow (16) must take place on word B MSB. A second borrowing condition is detected when the word A MSB is greater than the word B MSB (18) and the word B LSB is greater than the word A LSB (20). In this instance, a borrow (22) should take place on word A MSB through a shift right function. After borrowing, a subtraction (24) takes place by exclusive-or'ing word A and B MSBs. The result is reconstructed (26) through a shift right process into proper thermometer code format. If a borrowing condition exists, an appropriate LSB is translated (28, 30) before an LSB subtraction process (32) takes the resulting word A and word B LSBs and exclusively-or's them together. The result is reconstructed (34) through a shift right rotate left process to place the LSB in proper thermometer code format.
摘要翻译：减去具有最高有效字节（MSB）和最低有效字节（LSB）的两个温度计编码字，并检查借用条件。如果字B MSB大于字A MSB（12），字A LSB大于字B LSB（14），则检测到第一个借用条件。在这种情况下，借用（16）必须在B字母MSB上进行。当字A MSB大于字B MSB（18）并且字B LSB大于字A LSB（20）时，检测到第二借位条件。在这种情况下，借用（22）应通过转移权函数在A MSB上进行。借用后，通过排除A或B的MSBs来进行减法（24）。结果通过正确的转换重建（26）到适当的温度计代码格式。如果存在借用条件，则在LSB减法处理（32）将所得到的字A和字B LSB作为LSB之前，将它们排列在一起之前，转换适当的LSB（28,30）。通过右移旋转左进程重建（34）结果，将LSB置于合适的温度计代码格式。

4. 发明授权

US5789956A Low power flip-flop 失效
标题翻译：低功率触发器
公开(公告)号：US5789956A
公开(公告)日：1998-08-04
申请号：US451875
申请日：1995-05-26
申请人： Shivaling S. Mahant-Shetti , Robert J. Landers
发明人： Shivaling S. Mahant-Shetti , Robert J. Landers
IPC分类号： H03K3/3562 , H03K3/012 , H03K3/037 , H03K3/289 , H03K3/356
CPC分类号： H03K3/0372 , H03K3/012
摘要： A flip-flop circuit which includes a master section (1) having a pair of back to back connected inverters (5, 7) to form a latch circuit with their ground terminals connected together. The clock signal is coupled to the ground terminal of the inverters (5,7) to provide a negative gate to source voltage rather than an essentially zero gate to source voltage as used in prior art inverters to insure full turn off of the inverter transistors (40, 45) during their off periods and conserving power thereby. When the first phase of the clock signal goes high, the signal on the data line is fed to one side of the latch and the other side of the latch is coupled to ground or reference voltage. When the first phase of the clock then goes low, the signal from the data line is latched into the latch of the master section (1) and the other side of that latch is decoupled from ground. Also, when the first phase of the clock signal goes low and the second phase of the clock signal concurrently goes high, the signal latched in the latch of the master section (1) is fed to the slave section (3). The slave section (3) is identical to the master section (1) except that the clock signals received are of opposite phase or state to the clock signals received by the master section (1) and the input to the slave section (3) is the signal latched into the latch of the master section (1). The signal stored in the latch of the slave section (3) is the output of the flip-flop.
摘要翻译：一种触发器电路，其包括具有一对背对背连接的反相器（5,7）的主部分（1），以形成其接地端子连接在一起的锁存电路。时钟信号耦合到反相器（5,7）的接地端子以提供负的栅极到源极电压，而不是如现有技术的逆变器中使用的基本上为零的栅极 - 源极电压，以确保逆变器晶体管的全部关断（ 40，45），从而节省电力。当时钟信号的第一相位变高时，数据线上的信号被馈送到锁存器的一侧，并且锁存器的另一侧耦合到地或参考电压。当时钟的第一阶段然后变低时，来自数据线的信号被锁存到主控部分（1）的锁存器中，并且该锁存器的另一侧与地耦合。此外，当时钟信号的第一相位变低并且时钟信号的第二相位同时变高时，锁存在主器件部分（1）的锁存器中的信号被馈送到从部件（3）。从机部分（3）与主部分（1）相同，除了所接收的时钟信号与由主机部分（1）接收的时钟信号相反或相位相反，并且从机部分（3）的输入是该信号锁定在主控部分（1）的锁存器中。存储在从部分（3）的锁存器中的信号是触发器的输出。

5. 发明授权

US5723988A CMOS with parasitic bipolar transistor 失效
标题翻译： CMOS与寄生双极晶体管
公开(公告)号：US5723988A
公开(公告)日：1998-03-03
申请号：US139490
申请日：1993-10-20
申请人： Shivaling S. Mahant-Shetti , Mark G. Harward , Lawrence A. Arledge, Jr. , Ravishankar Sundaresan
发明人： Shivaling S. Mahant-Shetti , Mark G. Harward , Lawrence A. Arledge, Jr. , Ravishankar Sundaresan
IPC分类号： H01L27/06 , H03K17/567 , H03K19/08 , H03K19/0948
CPC分类号： H01L27/0623 , H03K17/567
摘要： A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.
摘要翻译：公开了一种使用现有的寄生双极器件结合CMOS和双极的优点的器件。由于器件同时具有高速能力同时保持低功率优点，所以可实现高的片上密度。

6. 发明授权

US5654981A Signal transmission system and method of operation 失效
标题翻译：信号传输系统及操作方法
公开(公告)号：US5654981A
公开(公告)日：1997-08-05
申请号：US718118
申请日：1996-09-18
申请人： Shivaling S. Mahant-Shetti , Robert J. Landers
发明人： Shivaling S. Mahant-Shetti , Robert J. Landers
IPC分类号： H04L25/02 , H04B1/38 , H04L5/16
CPC分类号： H04L25/0282 , H04L25/0286 , H04L25/0294
摘要： A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).
摘要翻译：提供了一种信号传输系统（10），其包括使用当前信号传输模式通过传输线（16）将信号发送到接收机电路（14）的发射机电路（12）。稳态电流由稳态电流源（22）提供。有源电流由有源电流源（20）提供。提供升压电路（18）以通过增加对传输线的电荷来减少与传输线（16）相关联的延迟，并且在沿着传输线（16）传播的信号的转变期间从传输线提供附加的放电路径。

7. 发明授权

US5528550A Apparatus, systems and methods for implementing memory embedded search arithmetic logic unit 失效
标题翻译：用于实现存储器嵌入式搜索算术逻辑单元的装置，系统和方法
公开(公告)号：US5528550A
公开(公告)日：1996-06-18
申请号：US69308
申请日：1993-05-28
申请人： Basavaraj Pawate , George Doddington , Shivaling S. Mahant-Shetti , Derek Smith
发明人： Basavaraj Pawate , George Doddington , Shivaling S. Mahant-Shetti , Derek Smith
IPC分类号： G06F12/00 , G06F7/575 , G06F17/30 , G11C13/00
CPC分类号： G06F7/575 , G06F15/7821 , G06F17/30982 , G06F9/3879 , G06F2207/4802 , G06F2207/4804
摘要： An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data. A broadcast memory 22 is provided which includes rows and columns of storage locations for holding control instructions. Search circuitry 26, 52 is provided which is operable to receive at least one word of data from data memory 20 and test the word against a preselected search test condition. Control circuitry 24 is operable in response to control instructions received from the broadcast memory 22 to control the transfer of the word of data from the data memory 20 to the search circuitry 26, 52 and the test of the word by the search circuitry 26, 52.
摘要翻译：提供了一个活动存储器14，其包括数据存储器20，数据存储器20包括用于保存数据的存储位置的行和列。提供广播存储器22，其包括用于保持控制指令的存储位置的行和列。提供了搜索电路26,52，其可操作以从数据存储器20接收至少一个数据字，并根据预选的搜索测试条件测试该字。控制电路24可响应于从广播存储器22接收的控制指令来操作，以控制数据字从数据存储器20传输到搜索电路26,52，以及由搜索电路26,52测试字。

8. 发明授权

US5479034A Method of making gate array base cell 失效
标题翻译：制造栅极阵列基体的方法
公开(公告)号：US5479034A
公开(公告)日：1995-12-26
申请号：US386613
申请日：1995-02-10
申请人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
发明人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/118 , H01L27/02
CPC分类号： H01L27/11807 , H01L21/8238
摘要： A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.
摘要翻译：可以容易地配置为高导电性晶体管器件或低导电性晶体管器件的栅阵列基电池包括例如通常为重掺杂n型硅或重掺杂p型硅的第一导电类型的护环区域。不同导电类型的沟道区域将护城河区域分成至少三个部分。在通道区域上方形成例如二氧化硅等绝缘层和栅极。例如，栅极可以由多晶硅形成。还公开了修改，变型，电路配置和说明性制造方法。

9. 发明授权

US5422581A Gate array cell with predefined connection patterns 失效
标题翻译：门阵列单元格具有预定义的连接模式
公开(公告)号：US5422581A
公开(公告)日：1995-06-06
申请号：US291639
申请日：1994-08-17
申请人： Shivaling S. Mahant-Shetti , Robert J. Landers
发明人： Shivaling S. Mahant-Shetti , Robert J. Landers
IPC分类号： H01L27/118 , H03K19/173
CPC分类号： H01L27/11807
摘要： A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.
摘要翻译：用于CMOS门阵列的基本单元设置有第一多个N沟道晶体管12,14,16，其中两个这样的N沟道晶体管串联耦合。具有串联耦合的两个这样的P沟道晶体管的第一多个P沟道晶体管50,52,54。这些晶体管在晶体管级互连以形成部分预接线电路。串联连接的N沟道晶体管（18,20），（22,24）和成对的串联P沟道晶体管（56,58）（60,62）的附加对也被提供并且在晶体管级互连以形成额外的部分预接线电路。通过添加额外的布线100,102，可以最终连接基座以形成多个不同的逻辑电路。

10. 发明授权

US4723228A Memory decoding circuit 失效
标题翻译：存储器解码电路
公开(公告)号：US4723228A
公开(公告)日：1988-02-02
申请号：US528205
申请日：1983-08-31
申请人： Ashwin H. Shah , James D. Gallia , Shivaling S. Mahant-Shetti
发明人： Ashwin H. Shah , James D. Gallia , Shivaling S. Mahant-Shetti
IPC分类号： G11C11/413 , G11C7/10 , G11C8/12 , G11C11/34 , G11C11/41 , G11C11/419 , G11C8/00
CPC分类号： G11C7/10 , G11C8/12
摘要： Column decoding is performed using multiply decoded subsets of column address bits bussed across the array to multiple first stage and second stage column multiplexers. That is, for example, in an 8k by 9 memory wherein each subarray contains 16 selectable columns at each bit position, two of the address bits would be fully decoded to provide four buss lines across the chip. Each column has a primary sense amplifier, controlled by one of these four decoded lines. The outputs of each set of four primary sense amplifiers are multiplexed into a secondary sense amplifier, (preferably on a local three-scale buss) and the output of each secondary sense amplifier is selected or deselected by four buss lines which are the decoded signals corresponding to the other two address bits which select one of 16 columns. Preferably multiplexing of the output of the secondary sense amplifiers is accomplished by a three-state buffer, so that the output of these buffers can be accomplished as a wired-or function.
摘要翻译：列解码使用跨阵列总线的列地址位的多位解码子集执行到多个第一级和第二级列复用器。也就是说，例如，在8k×9存储器中，每个子阵列在每个位位置包含16个可选列，地址位中的两个将被完全解码以在芯片上提供四条总线。每列具有由这四条解码线中的一条控制的初级读出放大器。每组四个主感测放大器的输出被复用到次级读出放大器（优选地在局部三级总线上），并且每个次级读出放大器的输出由对应的解码信号的四条母线选择或取消选择到另外两个选择16列之一的地址位。优选地，二次感测放大器的输出的多路复用由三态缓冲器实现，使得这些缓冲器的输出可以被实现为有线或功能。

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