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    • 4. 发明授权
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US06730563B2
    • 2004-05-04
    • US10365641
    • 2003-02-13
    • Akira Matsumura
    • Akira Matsumura
    • H01L218242
    • H01L27/10852H01L21/3212H01L27/10817H01L27/10894H01L27/10897H01L28/84H01L28/91
    • A rough polysilicon film located on the upper surface of an interlayer film is removed by a CMP process, so that storage nodes and an embedded TEOS film are formed. The embedded TEOS film is removed concurrently with the interlayer film located in a memory cell region by etching. An opening end of a groove, the upper surface of the embedded TEOS film and the upper surface of the interlayer film are arranged on substantially the same plane. In the memory cell region and a peripheral circuit region, a substantially flat interlayer insulation film is obtained. This solves the problems of a step, falling and the like in a semiconductor device including a capacitor element.
    • 通过CMP工艺去除位于层间膜的上表面上的粗多晶硅膜,从而形成存储节点和嵌入的TEOS膜。 通过蚀刻与位于存储单元区域中的层间膜同时去除嵌入的TEOS膜。 凹槽的开口端,嵌入的TEOS膜的上表面和层间膜的上表面布置在基本上相同的平面上。 在存储单元区域和外围电路区域中,获得基本平坦的层间绝缘膜。 这解决了包括电容器元件的半导体器件中的台阶,下落等问题。
    • 5. 发明授权
    • Method of fabricating an integrated circuit
    • 制造集成电路的方法
    • US06570233B2
    • 2003-05-27
    • US09901071
    • 2001-07-10
    • Akira Matsumura
    • Akira Matsumura
    • H01L21338
    • H01L29/66636H01L21/28525H01L21/76877H01L2924/0002H01L2924/00
    • The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.
    • 本发明提供了一种用于降低直接接触电阻并减少接头泄漏同时保持穿孔余量的技术。 提供一种半导体集成电路器件,包括:衬底; 形成在基板上的晶体管,其包括源极,漏极和控制从所述源极流向所述漏极的电流的栅极; 以及接触插塞,其电连接到所述源极和漏极中的至少一个并由包括掺杂剂的导电材料制成。 接触塞由至少第一层和第二层形成。 第一层与源极和漏极中的一个接触,并且由包括第一浓度的掺杂剂的所述材料制成。 第二层由包括低于第二浓度的第二浓度的掺杂剂的所述材料层形成。