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1. 发明授权

US08143175B2 Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US08143175B2
公开(公告)日：2012-03-27
申请号：US12435787
申请日：2009-05-05
申请人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
发明人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L21/0338 , H01L21/28123 , H01L21/31116 , H01L21/32137
摘要： The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein during a step for etching a material 12 to be etched using a mask pattern composed of a photoresist 15 and inorganic films 14 and 13 made of SiN, SiON, SiO and the like formed on the material 12 to be etched, a mixed gas formed of a halogen-based gas such as chlorine-containing gas or bromine-containing gas and at least one fluorine-containing gas selected from a group of fluorine-containing gases composed of CF4, CHF3, SF6 and NF3 is used to reduce the mask pattern and the processing dimension of the material to be etched substantially equally during processing of the material 12 to be etched.
摘要翻译：本发明提供了一种用于使用等离子体蚀刻装置在半导体衬底上进行布线处理的干蚀刻方法，其中进行布线处理而不引起布线的断开或偏转。本发明提供一种使用等离子体蚀刻装置对半导体衬底进行布线处理的干式蚀刻方法，其中在使用由光致抗蚀剂15和无机膜14和13构成的掩模图案来蚀刻要蚀刻的材料12的步骤期间，在被蚀刻材料12上形成的SiN，SiON，SiO等，由含氯气体或含溴气体的卤素系气体形成的混合气体和至少一种选自使用由CF4，CHF3，SF6和NF3组成的含氟气体组，在待蚀刻材料12的加工期间，基本上相同地减少掩模图案和待蚀刻材料的加工尺寸。

2. 发明申请

US20070218696A1 Dry etching method 审中-公开
标题翻译：干蚀刻法
公开(公告)号：US20070218696A1
公开(公告)日：2007-09-20
申请号：US11509736
申请日：2006-08-25
申请人： Kenichi Kuwabara , Satoshi Une , Tomoyoshi Ichimaru , Masamichi Sakaguchi , Naoki Yasui
发明人： Kenichi Kuwabara , Satoshi Une , Tomoyoshi Ichimaru , Masamichi Sakaguchi , Naoki Yasui
IPC分类号： H01L21/465
CPC分类号： H01L21/32137
摘要： The invention provides a method for processing vertical gate patterns while reducing the Si substrate recess dimension caused by overetching. The invention provides a dry etching method for processing a gate pattern by performing a main etching process (b) and then an overetching process on a gate pattern layer 12 of a semiconductor substrate 10, wherein the overetching process (c) is performed using a composite gas having added to an etching gas containing HBr gas a gas represented by a general formula of CxHy or at least one gas selected from CO and CO2 gases.
摘要翻译：本发明提供了一种在减少由过蚀刻引起的Si衬底凹陷尺寸的同时处理垂直栅极图案的方法。本发明提供一种通过在半导体衬底10的栅极图案层12上执行主蚀刻工艺（b）然后进行过蚀刻处理来进行栅极图案的干式蚀刻方法，其中过蚀刻工艺（c）使用复合材料已经添加到含有HBr气体的蚀刻气体的气体是由通式C x H y表示的气体或选自CO和CO 2气体的至少一种气体。

3. 发明申请

US20070207618A1 Dry etching method 审中-公开
标题翻译：干蚀刻法
公开(公告)号：US20070207618A1
公开(公告)日：2007-09-06
申请号：US11505292
申请日：2006-08-17
申请人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
发明人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0338 , H01L21/28123 , H01L21/31116 , H01L21/32137
摘要： The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein during a step for etching a material 12 to be etched using a mask pattern composed of a photoresist 15 and inorganic films 14 and 13 made of SiN, SiON, SiO and the like formed on the material 12 to be etched, a mixed gas formed of a halogen-based gas such as chlorine-containing gas or bromine-containing gas and at least one fluorine-containing gas selected from a group of fluorine-containing gases composed of CF4, CHF3, SF6 and NF3 is used to reduce the mask pattern and the processing dimension of the material to be etched substantially equally during processing of the material 12 to be etched.
摘要翻译：本发明提供了一种用于使用等离子体蚀刻装置在半导体衬底上进行布线处理的干蚀刻方法，其中进行布线处理而不引起布线的断开或偏转。本发明提供一种使用等离子体蚀刻装置对半导体衬底进行布线处理的干式蚀刻方法，其中在使用由光致抗蚀剂15和无机膜14和13构成的掩模图案来蚀刻要蚀刻的材料12的步骤期间，在被蚀刻材料12上形成的SiN，SiON，SiO等，由含氯气体或含溴气体的卤素系气体形成的混合气体和至少一种选自使用由CF 4，CHF 3，SF 6和NF 3 3构成的含氟气体组，在要蚀刻的材料12的处理期间，基本上相同地减小掩模图案和待蚀刻材料的加工尺寸。

4. 发明申请

US20130015158A1 DRY ETCHING METHOD 有权
标题翻译：干蚀刻方法
公开(公告)号：US20130015158A1
公开(公告)日：2013-01-17
申请号：US13210446
申请日：2011-08-16
申请人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
发明人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
IPC分类号： C23F1/02
CPC分类号： H01L21/28079 , H01J37/32192 , H01L21/31116 , H01L21/32137 , H01L29/66545
摘要： The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.
摘要翻译：本发明提供了一种干式蚀刻方法，其能够容易地提供在通过去除虚拟材料形成的沟槽和通孔处的称为顶部圆形的圆形顶部边缘部分。本发明的方法是通过去除其周围被层间氧化膜包围的虚拟材料形成沟槽或通孔的干蚀刻方法，该方法包括以下步骤：将虚拟材料蚀刻至预定深度，执行各向同性蚀刻虚拟材料蚀刻，并且在各向同性蚀刻之后除去虚拟材料的剩余部分。

5. 发明授权

US08580689B2 Plasma processing method 有权
标题翻译：等离子体处理方法
公开(公告)号：US08580689B2
公开(公告)日：2013-11-12
申请号：US13210446
申请日：2011-08-16
申请人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
发明人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
IPC分类号： H01L21/302
CPC分类号： H01L21/28079 , H01J37/32192 , H01L21/31116 , H01L21/32137 , H01L29/66545
摘要： The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.
摘要翻译：本发明提供了一种干式蚀刻方法，其能够容易地提供在通过去除虚拟材料形成的沟槽和通孔处的称为顶部圆形的圆形顶部边缘部分。本发明的方法是通过去除其周围被层间氧化膜包围的虚拟材料形成沟槽或通孔的干蚀刻方法，该方法包括以下步骤：将虚拟材料蚀刻至预定深度，执行各向同性蚀刻虚拟材料蚀刻，并且在各向同性蚀刻之后除去虚拟材料的剩余部分。

6. 发明授权

US07989330B2 Dry etching method 有权
标题翻译：干蚀刻法
公开(公告)号：US07989330B2
公开(公告)日：2011-08-02
申请号：US12512103
申请日：2009-07-30
申请人： Takeshi Shima , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
发明人： Takeshi Shima , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/02071 , H01L21/02115 , H01L21/02274
摘要： After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.
摘要翻译：在蚀刻多晶硅膜之后，当使用含有碳的等离子体在多晶硅膜的侧壁上形成由碳聚合物制成的保护膜时，在蚀刻条件下，使用含有卤素气体的等离子体蚀刻作为下部膜的金属材料，其中由于晶片温度的上升或处理压力的低压，挥发性提高，从而防止多晶硅膜的侧壁蚀刻和不均匀。此外，通过使用由碳聚合物制成的保护膜，在蚀刻金属材料时分散的金属物质不直接附着于多晶硅膜，而是可以简单地与由碳聚合物制成的保护膜一起除去问一步

7. 发明申请

US20100285669A1 DRY ETCHING METHOD 有权
标题翻译：干蚀刻方法
公开(公告)号：US20100285669A1
公开(公告)日：2010-11-11
申请号：US12512103
申请日：2009-07-30
申请人： Takeshi SHIMA , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
发明人： Takeshi SHIMA , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
IPC分类号： H01L21/3065
CPC分类号： H01L21/32139 , H01L21/02071 , H01L21/02115 , H01L21/02274
摘要： After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.
摘要翻译：在蚀刻多晶硅膜之后，当使用含有碳的等离子体在多晶硅膜的侧壁上形成由碳聚合物制成的保护膜时，在蚀刻条件下，使用含有卤素气体的等离子体蚀刻作为下部膜的金属材料，其中由于晶片温度的上升或处理压力的低压，挥发性提高，从而防止多晶硅膜的侧壁蚀刻和不均匀。此外，通过使用由碳聚合物制成的保护膜，在蚀刻金属材料时分散的金属物质不直接附着在多晶硅膜上，而是可以简单地与由碳聚合物制成的保护膜一起除去问一步

8. 发明申请

US20050189320A1 Plasma processing method 审中-公开
标题翻译：等离子体处理方法
公开(公告)号：US20050189320A1
公开(公告)日：2005-09-01
申请号：US11113026
申请日：2005-04-25
申请人： Tomoyoshi Ichimaru , Motohiko Yoshigai , Hideyuki Yamamoto , Shoji Ikuhara , Akira Kagoshima
发明人： Tomoyoshi Ichimaru , Motohiko Yoshigai , Hideyuki Yamamoto , Shoji Ikuhara , Akira Kagoshima
IPC分类号： H01L21/00 , C23F1/00
CPC分类号： H01L21/67253 , H01J37/32935 , H01L21/67069 , H01L21/67248
摘要： A plasma processing method for performing plasma processing on a sample in accordance with a process recipe with the sample being placed on a sample table in which each of a plurality of areas is temperature-controlled by a temperature controller. The process recipe includes a plurality of temperature setting parameters for the sample table, and the plasma processing is performed on the sample in accordance with the process recipe which is prepared for each of a plurality of process steps.
摘要翻译：一种等离子体处理方法，用于根据处理配方对样品进行等离子体处理，其中样品被放置在样本台上，其中多个区域中的每一个被温度控制器温度控制。处理配方包括用于样品台的多个温度设定参数，并且根据为多个处理步骤中的每一个准备的处理配方对样品执行等离子体处理。

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