专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08063669B2 Frequency synthesizer having a plurality of independent output tones 有权
标题翻译：具有多个独立输出音调的频率合成器
公开(公告)号：US08063669B2
公开(公告)日：2011-11-22
申请号：US12291255
申请日：2008-11-06
申请人： Saska Lindfors , Kari Stadius , Liangge Xu , Tapio Rapinoja , Jussi Ryynanen , Risto H. S. Kaunisto , Aarno Parssinen
发明人： Saska Lindfors , Kari Stadius , Liangge Xu , Tapio Rapinoja , Jussi Ryynanen , Risto H. S. Kaunisto , Aarno Parssinen
IPC分类号： H03B21/00
CPC分类号： G06F1/022
摘要： Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs.
摘要翻译：描述了一种装置，其包括频率源和多个时域直接数字合成器，每个时域直接数字合成器具有连接到频率源的输出的输入端和提供输出频率信号的输出。特定的时域直接数字合成器包括用作二阶多级噪声整形Σ-Δ调制器的Σ-Δ调制器。在一个示例性实施例中，Σ-Δ调制器输出提供用于切换包括延迟调制器的一部分的某些单位电容器的单位加权字，以产生时变延迟，该时变延迟具有直接对应于出现在多个相位累加器输出。

2. 发明申请

US20100109714A1 Frequency synthesizer having a plurality of independent output tones 有权
标题翻译：具有多个独立输出音调的频率合成器
公开(公告)号：US20100109714A1
公开(公告)日：2010-05-06
申请号：US12291255
申请日：2008-11-06
申请人： Saska Lindfors , Kari Stadius , Liangge Xu , Tapio Rapinoja , Jussi Ryynanen , Risto H.S. Kaunisto , Aarno Parssinen
发明人： Saska Lindfors , Kari Stadius , Liangge Xu , Tapio Rapinoja , Jussi Ryynanen , Risto H.S. Kaunisto , Aarno Parssinen
IPC分类号： H03B21/00
CPC分类号： G06F1/022
摘要： Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs.
摘要翻译：描述了一种装置，其包括频率源和多个时域直接数字合成器，每个时域直接数字合成器具有连接到频率源的输出的输入端和提供输出频率信号的输出。特定的时域直接数字合成器包括用作二阶多级噪声整形Σ-Δ调制器的Σ-Δ调制器。在一个示例性实施例中，Σ-Δ调制器输出提供用于切换包括延迟调制器的一部分的某些单位电容器的单位加权字，以产生时变延迟，该时变延迟具有直接对应于出现在多个相位累加器输出。

3. 发明申请

US20100029210A1 Method, apparatus and computer program for estimating spectrum using a folding ADC 审中-公开
标题翻译：使用折叠ADC估计频谱的方法，装置和计算机程序
公开(公告)号：US20100029210A1
公开(公告)日：2010-02-04
申请号：US12148859
申请日：2008-04-22
申请人： Mikko Kaltiokallio , Saska Lindfors , Jussi Ryynanen
发明人： Mikko Kaltiokallio , Saska Lindfors , Jussi Ryynanen
IPC分类号： H04B17/00 , G05B23/00
CPC分类号： H03J1/0091
摘要： To find frequency slots over which a cognitive radio can send an opportunistic transmission, a wideband spectrum is searched with a lower resolution to identify bandwidth slices having low or no signal levels. The identified bandwidth slices are searched with a higher resolution candidate frequency slices are selected as those bandwidth slices having least signal levels after the higher resolution searching, and ranked from lowest signal level to highest. A spectrum detection algorithm is executed on the selected candidate frequency slices in the order of the rank until it is decided that one of them has sufficiently free spectrum. A transmission is then opportunistically sent on the decided candidate frequency slice. Ongoing to the searching, intermittent signals are detected and a band about them is searched with the lower resolution to determine if the band about the detected intermittent signal is an identified bandwidth slice. Various techniques are shown for how the fine search is conducted.
摘要翻译：为了找到认知无线电可以在其上发送机会性传输的频率时隙，以较低的分辨率搜索宽带频谱以识别具有低信号级别或没有信号级别的带宽片段。用更高分辨率的候选频率片段搜索所识别的带宽片，作为在更高分辨率搜索之后具有最小信号电平的那些带宽片，并且从最低信号电平到最高排列。在所选择的候选频率片上以等级的顺序执行频谱检测算法，直到确定其中的一个具有足够的自由频谱。然后在所确定的候选频率片上机会地发送传输。进行搜索时，检测到间歇信号，并以较低的分辨率搜索关于它们的频带，以确定关于检测到的间歇信号的频带是否是识别的带宽片。显示了如何进行精细搜索的各种技术。

4. 发明授权

US06438366B1 Method and circuit for sampling a signal at high sampling frequency 有权
标题翻译：采样频率高的信号采样方法和电路
公开(公告)号：US06438366B1
公开(公告)日：2002-08-20
申请号：US09316357
申请日：1999-05-21
申请人： Saska Lindfors , Aarno Pärssinen , Kari Halonen
发明人： Saska Lindfors , Aarno Pärssinen , Kari Halonen
IPC分类号： H03H1702
CPC分类号： H03H19/004 , H03H17/0291
摘要： Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It comprises a first sampler circuit (302, 510, 803, 910) coupled to the input, a second sampler circuit (303, 520, 804, 920) coupled to the input, a buffering component (309, 509, 809, 903, 904) coupled to the output and buffer switching means (305-307, 514, 515, 811-818, 914, 915, 924, 925, 934, 935, 944, 945, 954, 955, 964, 965, 974, 975, 984, 985). The buffer switching means are arranged to respond to a buffering command (fs/N, A, B) by coupling said first sampler circuit and said second sampler circuit to said buffering component.
摘要翻译：电路（300,500,800,900）具有输入（301,501,801,802,901,902）和输出（311,502，OUT，I-OUT，Q-OUT）。电路对耦合到具有一定输入频率的输入的输入信号进行采样，并将输入信号转换成输出端的某一输出频率，输出频率低于输入频率。它包括耦合到输入的第一采样器电路（302,510,803,910），耦合到输入的第二采样器电路（303,520,804,920），缓冲部件（309,509,809,903,904））耦合到输出和缓冲器切换装置（305-307,514,515,811-818,914,915,924,925,934,935,944,945,954,955,964,965,974,975,984,984 缓冲器切换装置被布置成通过将所述第一采样器电路和所述第二采样器电路耦合到所述缓冲部件来响应缓冲命令（fs / N，A，B）。

5. 发明授权

US06453309B1 Method for correcting errors in parallel A/D conversion, corrector and parallel A/D converter 失效
标题翻译：并行A / D转换，校正器和并行A / D转换器校正误差的方法
公开(公告)号：US06453309B1
公开(公告)日：2002-09-17
申请号：US09310640
申请日：1999-05-12
申请人： Asko Kananen , Ari Paasio , Saska Lindfors , Kari Halonen
发明人： Asko Kananen , Ari Paasio , Saska Lindfors , Kari Halonen
IPC分类号： G06F9445
CPC分类号： H03M1/0809 , H03M1/365
摘要： The invention pertains to a method and corrector (IC6) for correcting an error in a parallel analog-to-digital conversion. Such a correctable error is caused by uncertainties in the reading of the states of parallel comparing elements (IC1, IC2, IC3, IC4) in the converter, said uncertainties being brought about by nonideality, such as non-simultaneous state latching. This error is corrected using a nonlinear cellular neural network preferably such that the real level of the phenomenon compared by means of comparing elements (IC1, IC2, IC3, IC4) is estimated by estimating the states corresponding to correct reading of the comparing elements (IC1, IC2, IC3, IC4) read temporally or otherwise erroneously.
摘要翻译：本发明涉及用于校正并行模数转换中的误差的方法和校正器（IC6）。这种可校正误差是由转换器中的并行比较元件（IC1，IC2，IC3，IC4）的状态读数的不确定性引起的，所述不确定性是由诸如非同时状态锁存之类的非等级引起的。使用非线性细胞神经网络来校正该误差，优选地，通过比较元件（IC1，IC2，IC3，IC4）比较元件（IC1，IC2，IC3，IC4）比较的现象的实际水平是通过估计与比较元件（IC1，，IC2，IC3，IC4）在时间上或其他方式错误地读取。

6. 发明授权

US06313775B1 Delta-sigma modulator with two-step quantization, and method for using two-step quantization in delta-sigma modulation 有权
标题翻译：具有两步量化的Δ-Σ调制器以及在Δ-Σ调制中使用两步量化的方法
公开(公告)号：US06313775B1
公开(公告)日：2001-11-06
申请号：US09652749
申请日：2000-08-31
申请人： Saska Lindfors , Kari Halonen
发明人： Saska Lindfors , Kari Halonen
IPC分类号： H03M382
CPC分类号： H03M3/424 , H03M1/167
摘要： A delta-sigma modulator for converting an analog input signal into a digital output signal comprises a modulator input (501) and a first analog to digital converter (504) coupled to the modulator input (501). The first analog to digital converter has a first analog input and a first digital output. The delta-sigma modulator further comprises an error quantization unit (505, 506, 507) coupled to the first digital output for determining the quantization error caused by the first analog to digital converter (504). Additionally it comprises first signal combining means (508, 708, 802) for combining the outputs of the first analog to digital converter and said error quantization unit to form the digital output signal.
摘要翻译：用于将模拟输入信号转换为数字输出信号的Δ-Σ调制器包括耦合到调制器输入（501）的调制器输入（501）和第一模数转换器（504）。第一模数转换器具有第一模拟输入和第一数字输出。 Δ-Σ调制器还包括耦合到第一数字输出的误差量化单元（505,506,507），用于确定由第一模数转换器（504）引起的量化误差。另外，它包括用于组合第一模数转换器和所述误差量化单元的输出以形成数字输出信号的第一信号组合装置（508,708,802）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式