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1. 发明申请

US20050125481A1 Adder circuit with sense-amplifier multiplexer front-end 有权
标题翻译：加法器电路带有读出放大器多路复用器前端
公开(公告)号：US20050125481A1
公开(公告)日：2005-06-09
申请号：US10728127
申请日：2003-12-04
申请人： Sanu Mathew , Mark Anders , Ram Krishnamurthy , Sapumal Wijeratne
发明人： Sanu Mathew , Mark Anders , Ram Krishnamurthy , Sapumal Wijeratne
IPC分类号： G06F7/50 , G06F7/506 , G06F7/507
CPC分类号： G06F7/507 , G06F7/506
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译：一个加法器电路包括多个选择器和一个加法器。选择器为加法器提供多个输入数据位。每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

2. 发明申请

US20060253523A1 Sparse tree adder circuit 有权
公开(公告)号：US20060253523A1
公开(公告)日：2006-11-09
申请号：US11123702
申请日：2005-05-09
申请人： Mark Anders , Sanu Mathew , Nanda Siddaiah , Sapumal Wijeratne
发明人： Mark Anders , Sanu Mathew , Nanda Siddaiah , Sapumal Wijeratne
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/508
摘要： An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.

3. 发明申请

US20150086007A1 COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
标题翻译：紧凑型低功耗高级加密标准电路
公开(公告)号：US20150086007A1
公开(公告)日：2015-03-26
申请号：US14035508
申请日：2013-09-24
申请人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
发明人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
IPC分类号： H04L9/30
CPC分类号： H04L9/0631 , H04L2209/24
摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.
摘要翻译：公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。在一个实施例中，装置包括具有替换盒和累加器的加密单元。替代方案是对每个时钟周期的一个字节执行替换操作。累加器将累积四个字节，并在四个时钟周期内执行混合列操作。加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

4. 发明申请

US20080181295A1 Method and apparatus for video processing 有权
标题翻译：视频处理方法和装置
公开(公告)号：US20080181295A1
公开(公告)日：2008-07-31
申请号：US11699241
申请日：2007-01-29
申请人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
发明人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
IPC分类号： H04B1/66
CPC分类号： H04N19/436 , H04N19/43
摘要： In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括使用冗余二进制数学压缩视频数据的方法。描述和要求保护其他实施例。

5. 发明申请

US20080072128A1 DISTRIBUTED RING CONTROL CIRCUITS FOR VITERBI TRACEBACK 有权
标题翻译：用于VITERBI跟踪的分布式环控制电路
公开(公告)号：US20080072128A1
公开(公告)日：2008-03-20
申请号：US11860493
申请日：2007-09-24
申请人： Mark Anders , Sanu Mathew , Ram Krishnamurthy
发明人： Mark Anders , Sanu Mathew , Ram Krishnamurthy
IPC分类号： H03M13/41 , G11C19/00
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译：移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。

6. 发明授权

US09699096B2 Priority-based routing 有权
公开(公告)号：US09699096B2
公开(公告)日：2017-07-04
申请号：US14141356
申请日：2013-12-26
申请人： Sudhir Satpathy , Himanshu Kaul , Mark Anders , Sanu Mathew , Gregory Chen , Ram Krishnamurthy
发明人： Sudhir Satpathy , Himanshu Kaul , Mark Anders , Sanu Mathew , Gregory Chen , Ram Krishnamurthy
IPC分类号： H04L12/833 , H04L12/725 , H04L12/865 , H04L12/933 , H04L12/875
CPC分类号： H04L47/2458 , H04L45/30 , H04L47/56 , H04L47/6275 , H04L49/109
摘要： Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.

7. 发明申请

US20150188829A1 PRIORITY-BASED ROUTING 有权
标题翻译：优先级路由
公开(公告)号：US20150188829A1
公开(公告)日：2015-07-02
申请号：US14141356
申请日：2013-12-26
申请人： Sudhir Satpathy , Himanshu Kaul , Mark Anders , Sanu Mathew , Gregory Chen , Ram Krishnamurthy
发明人： Sudhir Satpathy , Himanshu Kaul , Mark Anders , Sanu Mathew , Gregory Chen , Ram Krishnamurthy
IPC分类号： H04L12/833 , H04L12/933 , H04L12/725
CPC分类号： H04L47/2458 , H04L45/30 , H04L47/56 , H04L47/6275 , H04L49/109
摘要： Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.
摘要翻译：这里公开了配置用于基于优先级路由的路由器。路由器被配置为接收多个分组，其中每个分组被分配优先级值。路由器包括配置为选择具有最高优先级值的分组的输出电路。输出电路被配置为将所选择的分组的优先级值转发给第二路由器。输出电路被配置为当第一路由器和第二路由器之间的链路可用时将所选择的分组传送到第二路由器。

8. 发明授权

US08265135B2 Method and apparatus for video processing 有权
标题翻译：视频处理方法和装置
公开(公告)号：US08265135B2
公开(公告)日：2012-09-11
申请号：US11699241
申请日：2007-01-29
申请人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
发明人： Mark Anders , Himanshu Kaul , Sanu Mathew , Steven Hsu , Amit Agarwal , Ram Krishnamurthy
IPC分类号： G06F21/00
CPC分类号： H04N19/436 , H04N19/43
摘要： In one embodiment, the invention includes a method for compressing video data using redundant binary mathematics. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括使用冗余二进制数学压缩视频数据的方法。描述和要求保护其他实施例。

9. 发明申请

US20070230606A1 Viterbi traceback 审中-公开
标题翻译：维特比追溯
公开(公告)号：US20070230606A1
公开(公告)日：2007-10-04
申请号：US11395108
申请日：2006-03-31
申请人： Mark Anders , Ram Krishnamurthy , Sanu Mathew
发明人： Mark Anders , Ram Krishnamurthy , Sanu Mathew
IPC分类号： H04L23/02
CPC分类号： H03M13/4169 , H03M13/6569
摘要： In accordance with some embodiments, a traceback unit with traceback and path memories is provided.
摘要翻译：根据一些实施例，提供具有回溯和路径存储器的回溯单元。

10. 发明申请

US20060221724A1 Data converter and a delay threshold comparator 失效
标题翻译：数据转换器和延迟阈值比较器
公开(公告)号：US20060221724A1
公开(公告)日：2006-10-05
申请号：US11094811
申请日：2005-03-31
申请人： Atul Maheshwari , Sanu Mathew , Mark Anders , Ram Krishnamurthy
发明人： Atul Maheshwari , Sanu Mathew , Mark Anders , Ram Krishnamurthy
IPC分类号： G11C7/06
CPC分类号： G06F9/3869 , G06F7/74
摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.
摘要翻译：对于一个所公开的实施例，转换器将2个N位数据转换为指示具有预定逻辑值的数据中的位数的N位值。转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。基于比较器的输出产生N位值。对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号值。比较器然后基于延迟信号产生位值。

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