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1. 发明授权

US08158465B2 Vertical coffee-stain method for forming self-organized line structures 有权
标题翻译：用于形成自组织线结构的垂直咖啡染色方法
公开(公告)号：US08158465B2
公开(公告)日：2012-04-17
申请号：US12484992
申请日：2009-06-15
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L21/336
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L51/0022 , H01L51/0508
摘要： A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：用于生产自组织线结构的“垂直”咖啡染色方法和其它非常细小的特征，其包括将目标结构设置在由分散在液体溶剂中的细颗粒溶质构成的溶液中，使得“水线”由溶液的上（液/空）表面在基材的目标线性表面区域上。然后使溶剂以预定的速率蒸发，使得一部分溶质在由后退水线接触的基底表面的直线部分上形成自组织的“咖啡污渍”线结构。选择底物和染色溶液使得液体溶剂对基底表面的吸引力比其本身具有更强的吸引力以产生所需的钉扎和向上弯曲的水线。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

2. 发明授权

US07867916B2 Horizontal coffee-stain method using control structure to pattern self-organized line structures 有权
标题翻译：使用控制结构的水平咖啡染色方法来模拟自组织线结构
公开(公告)号：US07867916B2
公开(公告)日：2011-01-11
申请号：US12485007
申请日：2009-06-15
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L51/40 , H01L21/84 , H01L21/461 , H01L21/469
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L29/40 , H01L51/0022 , H01L51/0508
摘要： A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：一种用于生产自组织线结构和其它非常精细特征的改进的咖啡染色方法，其涉及在目标基底上设置溶液池，然后使用接触水坑上表面的控制结构来控制熔池的外围边界形状。溶液由分散在液体溶剂润湿剂中的细颗粒溶质组成，并被固定到靶基质和对照结构两者上。然后使溶剂以预定的速率蒸发，使得溶质的一部分在目标衬底表面上形成与周边水泥边界接触的自组织的“咖啡污渍”线结构。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

3. 发明授权

US08268725B2 Horizontal coffee-stain method using control structure to pattern self-organized line structures 有权
标题翻译：使用控制结构的水平咖啡染色方法来模拟自组织线结构
公开(公告)号：US08268725B2
公开(公告)日：2012-09-18
申请号：US12900417
申请日：2010-10-07
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L21/288
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L29/40 , H01L51/0022 , H01L51/0508
摘要： A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：一种用于生产自组织线结构和其它非常精细特征的改进的咖啡染色方法，其涉及在目标基底上设置溶液池，然后使用接触水坑上表面的控制结构来控制熔池的外围边界形状。溶液由分散在液体溶剂润湿剂中的细颗粒溶质组成，并被固定到靶基质和对照结构两者上。然后使溶剂以预定的速率蒸发，使得溶质的一部分在目标衬底表面上形成与周边水泥边界接触的自组织的“咖啡污渍”线结构。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

4. 发明申请

US20100317160A1 HORIZONTAL COFFEE-STAIN METHOD USING CONTROL STRUCTURE TO PATTERN SELF-ORGANIZED LINE STRUCTURES 有权
标题翻译：使用控制结构绘制自组织线结构的水平咖啡 -
公开(公告)号：US20100317160A1
公开(公告)日：2010-12-16
申请号：US12485007
申请日：2009-06-15
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L21/336 , B05D3/02
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L29/40 , H01L51/0022 , H01L51/0508
摘要： A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：一种用于生产自组织线结构和其它非常精细特征的改进的咖啡染色方法，其涉及在目标基底上设置溶液池，然后使用接触水坑上表面的控制结构来控制熔池的外围边界形状。溶液由分散在液体溶剂润湿剂中的细颗粒溶质组成，并被固定到靶基质和对照结构两者上。然后使溶剂以预定的速率蒸发，使得溶质的一部分在目标衬底表面上形成与周边水泥边界接触的自组织的“咖啡污渍”线结构。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

5. 发明申请

US20110027946A1 Horizontal Coffee-Stain Method Using Control Structure To Pattern Self-Organized Line Structures 有权
标题翻译：使用控制结构对自组织线结构进行水平咖啡染色方法
公开(公告)号：US20110027946A1
公开(公告)日：2011-02-03
申请号：US12900417
申请日：2010-10-07
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L21/336 , B05D5/00
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L29/40 , H01L51/0022 , H01L51/0508
摘要： A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：一种用于生产自组织线结构和其它非常精细特征的改进的咖啡染色方法，其涉及在目标基底上设置溶液池，然后使用接触水坑上表面的控制结构来控制熔池的外围边界形状。溶液由分散在液体溶剂润湿剂中的细颗粒溶质组成，并被固定到靶基质和对照结构两者上。然后使溶剂以预定的速率蒸发，使得溶质的一部分在目标衬底表面上形成与周边水泥边界接触的自组织的“咖啡污渍”线结构。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

6. 发明申请

US20100317159A1 Vertical Coffee-Stain Method For Forming Self-Organized Line Structures 有权
标题翻译：用于形成自组织线结构的垂直咖啡 - 污渍方法
公开(公告)号：US20100317159A1
公开(公告)日：2010-12-16
申请号：US12484992
申请日：2009-06-15
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L21/336 , B05D5/12
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L51/0022 , H01L51/0508
摘要： A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：用于生产自组织线结构的“垂直”咖啡染色方法和其它非常细小的特征，其包括将目标结构设置在由分散在液体溶剂中的细颗粒溶质构成的溶液中，使得“水线”由溶液的上（液/空）表面在基材的目标线性表面区域上。然后使溶剂以预定的速率蒸发，使得一部分溶质在由后退水线接触的基底表面的直线部分上形成自组织的“咖啡污渍”线结构。选择底物和染色溶液使得液体溶剂对基底表面的吸引力比其本身具有更强的吸引力以产生所需的钉扎和向上弯曲的水线。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

7. 发明申请

US20120175616A1 Thin Film Field Effect Transistor with Dual Semiconductor Layers 有权
公开(公告)号：US20120175616A1
公开(公告)日：2012-07-12
申请号：US13426518
申请日：2012-03-21
申请人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
发明人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/78606 , H01L29/78645
摘要： A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.

8. 发明申请

US20120007079A1 Thin Film Field Effect Transistor with Dual Semiconductor Layers 有权
标题翻译：具有双半导体层的薄膜场效应晶体管
公开(公告)号：US20120007079A1
公开(公告)日：2012-01-12
申请号：US13239078
申请日：2011-09-21
申请人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
发明人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
IPC分类号： H01L29/04 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/78606 , H01L29/78645
摘要： A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.
摘要翻译：公开了薄膜场效应晶体管，其提供改进的基于时间的信道稳定性。场效应晶体管包括由绝缘体隔开的第一和第二无序半导体层。在一个实施例中，载流子注入端子设置在最靠近栅极端子的薄半导体层中。在薄半导体层中形成电场。在足够的场强下，电场延伸到与源极和漏极端子接触的第二半导体层。在足够的场强下，在第二半导体层中建立通道，允许电流在源极和漏极端子之间流动。在一定的栅极电压之上，在第一半导体层中感应出足够的自由电荷，使得场不延伸到第二半导体中，有效地关闭源极和漏极之间的电流。可以获得单器件转换检测（以及其他应用）。

9. 发明申请

US20110147742A1 Thin Film Field Effect Transistor with Dual Semiconductor Layers 有权
标题翻译：具有双半导体层的薄膜场效应晶体管
公开(公告)号：US20110147742A1
公开(公告)日：2011-06-23
申请号：US12642132
申请日：2009-12-18
申请人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
发明人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/78606 , H01L29/78645
摘要： A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.
摘要翻译：公开了薄膜场效应晶体管，其提供改进的基于时间的信道稳定性。场效应晶体管包括由绝缘体隔开的第一和第二无序半导体层。在一个实施例中，载流子注入端子设置在最靠近栅极端子的薄半导体层中。在薄半导体层中形成电场。在足够的场强下，电场延伸到与源极和漏极端子接触的第二半导体层。在足够的场强下，在第二半导体层中建立通道，允许电流在源极和漏极端子之间流动。在一定的栅极电压之上，在第一半导体层中感应出足够的自由电荷，使得场不延伸到第二半导体中，有效地关闭源极和漏极之间的电流。可以获得单器件转换检测（以及其他应用）。

10. 发明授权

US08288799B2 Thin film field effect transistor with dual semiconductor layers 有权
公开(公告)号：US08288799B2
公开(公告)日：2012-10-16
申请号：US13426518
申请日：2012-03-21
申请人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
发明人： Sanjiv Sambandan , Ana Claudia Arias , Gregory Lewis Whiting
IPC分类号： H01L27/148 , H01L21/3205
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/78606 , H01L29/78645
摘要： A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.

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