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1. 发明申请

US20070156954A1 Method and apparatus to maintain data integrity in disk cache memory during and after periods of cache inaccessiblity 有权
标题翻译：在高速缓存不可访问期间和之后，在磁盘高速缓冲存储器中保持数据完整性的方法和装置
公开(公告)号：US20070156954A1
公开(公告)日：2007-07-05
申请号：US11321434
申请日：2005-12-29
申请人： Sanjeev Trika , Michael Eschmann , Jeanna Matthews , Vasudevan Srinivasan
发明人： Sanjeev Trika , Michael Eschmann , Jeanna Matthews , Vasudevan Srinivasan
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F11/1471 , G06F12/0866 , G06F2201/82
摘要： A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
摘要翻译：易失性或非易失性缓存存储器可以缓存大容量存储设备读取数据并写入数据。高速缓冲存储器可能变得不可访问，并且I / O操作可能会绕过高速缓冲存储器直接进入大容量存储设备。可以维护写入操作的日志，以在高速缓存存储器可用时更新缓冲存储器。

2. 发明申请

US20050138289A1 Virtual cache for disk cache insertion and eviction policies and recovery from device errors 审中-公开
标题翻译：用于磁盘缓存插入和撤销策略的虚拟缓存以及设备错误的恢复
公开(公告)号：US20050138289A1
公开(公告)日：2005-06-23
申请号：US10739608
申请日：2003-12-18
申请人： Robert Royer , Sanjeev Trika , Jeanna Matthews , John Garney , Michael Eschmann
发明人： Robert Royer , Sanjeev Trika , Jeanna Matthews , John Garney , Michael Eschmann
IPC分类号： G06F11/14 , G06F12/00 , G06F12/08
CPC分类号： G06F12/121 , G06F11/1471 , G06F12/0866 , G06F2201/84 , G06F2212/311 , G06F2212/466
摘要： Processor-based systems may include a disk cache to increase system performance in a system that includes a processor and a disk drive. The disk cache may include physical cache lines and virtual cache lines to improve cache insertion and eviction policies. The virtual cache lines may also be useful when recovering from failed requests.
摘要翻译：基于处理器的系统可以包括磁盘缓存，以在包括处理器和磁盘驱动器的系统中提高系统性能。磁盘高速缓存可以包括物理高速缓存行和虚拟高速缓存行，以改善缓存插入和逐出策略。从失败的请求中恢复时，虚拟缓存线也可能很有用。

3. 发明申请

US20060129763A1 Virtual cache for disk cache insertion and eviction policies and recovery from device errors 审中-公开
标题翻译：用于磁盘缓存插入和撤销策略的虚拟缓存以及设备错误的恢复
公开(公告)号：US20060129763A1
公开(公告)日：2006-06-15
申请号：US11352162
申请日：2006-02-10
申请人： Robert Royer , Sanjeev Trika , Jeanna Matthews , John Garney , Michael Eschmann
发明人： Robert Royer , Sanjeev Trika , Jeanna Matthews , John Garney , Michael Eschmann
IPC分类号： G06F13/00
CPC分类号： G06F12/121 , G06F11/1471 , G06F12/0866 , G06F2201/84 , G06F2212/311 , G06F2212/466
摘要： Processor-based systems may include a disk cache to increase system performance in a system that includes a processor and a disk drive. The disk cache may include physical cache lines and virtual cache lines to improve cache insertion and eviction policies. The virtual cache lines may also be useful when recovering from failed requests.
摘要翻译：基于处理器的系统可以包括磁盘缓存，以在包括处理器和磁盘驱动器的系统中提高系统性能。磁盘高速缓存可以包括物理高速缓存行和虚拟高速缓存行，以改善缓存插入和逐出策略。从失败的请求中恢复时，虚拟缓存线也可能很有用。

4. 发明申请

US20070156955A1 Method and apparatus for queuing disk drive access requests 审中-公开
标题翻译：排队磁盘驱动器访问请求的方法和装置
公开(公告)号：US20070156955A1
公开(公告)日：2007-07-05
申请号：US11323780
申请日：2005-12-30
申请人： Robert Royer , Michael Eschmann , Amber Huffman , Knut Grimsrud , Sanjeev Trika , Brian Dees
发明人： Robert Royer , Michael Eschmann , Amber Huffman , Knut Grimsrud , Sanjeev Trika , Brian Dees
IPC分类号： G06F13/00
CPC分类号： G06F13/387
摘要： A method includes receiving a request to access a disk drive. The request has a size. The method further includes selecting a queue, based at least in part on the size of the request, from among a plurality of queues, and assigning the request to the selected queue.
摘要翻译：一种方法包括接收访问磁盘驱动器的请求。请求有一个大小。所述方法还包括至少部分地基于所述请求的大小从多个队列中选择队列，并将所述请求分配给所选择的队列。

5. 发明申请

US20050144396A1 Coalescing disk write back requests 审中-公开
标题翻译：合并磁盘回写请求
公开(公告)号：US20050144396A1
公开(公告)日：2005-06-30
申请号：US10751258
申请日：2003-12-31
申请人： Michael Eschmann , Jeanna Matthews , John Garney , Robert Royer
发明人： Michael Eschmann , Jeanna Matthews , John Garney , Robert Royer
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0866
摘要： Cache write back requests may be coalesced to reduce disk accesses and improve overall system performance in some embodiments of the present invention. Contiguous and non-contiguous data from more than one cache line may be coalesced into a single write back request and written back in one atomic write to the disk drive. This data may also be flushed from the disk cache in one request.
摘要翻译：缓存回写请求可以被合并以减少磁盘访问并提高本发明的某些实施例中的整体系统性能。来自多个高速缓存行的连续和不连续的数据可以被合并到单个回写请求中，并且以一个原子写入写回到磁盘驱动器。也可以在一个请求中从磁盘缓存刷新该数据。

6. 发明申请

US20050278486A1 Merging write-back and write-through cache policies 有权
标题翻译：合并回写和直写缓存策略
公开(公告)号：US20050278486A1
公开(公告)日：2005-12-15
申请号：US10867884
申请日：2004-06-15
申请人： Sanjeev Trika , John Garney , Michael Eschmann
发明人： Sanjeev Trika , John Garney , Michael Eschmann
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0866
摘要： In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain embodiments, the cache may store data according to a first cache policy and a second cache policy. A determination of whether to store data according to the first or second policies may be dependent upon an amount of dirty data in the cache, in certain embodiments. In certain embodiments, the cache may include at least one portion reserved for clean data.
摘要翻译：在一个实施例中，本发明包括如果将数据插入诸如与该磁盘相关联的磁盘高速缓存的高速缓存中时将数据写入到磁盘的方法，将导致满足或超过高速缓存中的脏数据的阈值。此外，在某些实施例中，高速缓存可以根据第一高速缓存策略和第二高速缓存策略来存储数据。在某些实施例中，根据第一或第二策略是否存储数据的确定可以取决于高速缓存中的脏数据量。在某些实施例中，高速缓存可以包括为干净数据保留的至少一个部分。

7. 发明申请

US20070192537A1 Request processing order in a cache 审中-公开
标题翻译：在缓存中请求处理顺序
公开(公告)号：US20070192537A1
公开(公告)日：2007-08-16
申请号：US11788607
申请日：2007-04-20
申请人： John Garney , Robert Royer , Michael Eschmann , Daniel Nemiroff
发明人： John Garney , Robert Royer , Michael Eschmann , Daniel Nemiroff
IPC分类号： G06F12/00 , G06F13/00 , G06F12/14
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0656 , G06F3/0674
摘要： A method and apparatus for preserving the processing order of some requests in a system is disclosed. The method may include blocking requests from executing based on a blocked count data field, blocking list data field, and a last request data field. The apparatus may include a system or a memory device.
摘要翻译：公开了一种用于保持系统中某些请求的处理顺序的方法和装置。该方法可以包括基于阻塞的计数数据字段，阻塞列表数据字段和最后一个请求数据字段阻止执行请求。该装置可以包括系统或存储装置。

8. 发明申请

US20050138281A1 Request processing order in a cache 审中-公开
标题翻译：在缓存中请求处理顺序
公开(公告)号：US20050138281A1
公开(公告)日：2005-06-23
申请号：US10739921
申请日：2003-12-18
申请人： John Garney , Robert Royer , Michael Eschmann , Daniel Nemiroff
发明人： John Garney , Robert Royer , Michael Eschmann , Daniel Nemiroff
IPC分类号： G06F3/06 , G06F12/00
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0656 , G06F3/0674
摘要： A method and apparatus for preserving the processing order of some requests in a system is disclosed. The method may include blocking requests from executing based on a blocked count data field, blocking list data field, and a last request data field. The apparatus may include a system or a memory device.
摘要翻译：公开了一种用于保持系统中某些请求的处理顺序的方法和装置。该方法可以包括基于阻塞的计数数据字段，阻塞列表数据字段和最后一个请求数据字段阻止执行请求。该装置可以包括系统或存储装置。

9. 发明授权

US5511069A Method and apparatus for controlling a communication device through a modem processor 失效
标题翻译：用于通过调制解调器处理器控制通信设备的方法和装置
公开(公告)号：US5511069A
公开(公告)日：1996-04-23
申请号：US269068
申请日：1994-06-30
申请人： David G. England , Michael Eschmann , Cecil Moore
发明人： David G. England , Michael Eschmann , Cecil Moore
IPC分类号： H04L5/14 , H04B1/56
CPC分类号： H04L5/1415
摘要： A method and apparatus for a processor of a computer system to control a communication device through a bus interface having six interconnects. The bus interface's first interconnect is a transmission and reception interconnect that allows the computer system to transmit and receive signals from a communication device (such as a telephone line or a radio transceiver). The second interconnect is a primary processor communication interconnect which serves as the primary communication route between the processor and a radio transceiver's microcontroller, and which enables the processor to control the various components of the radio transceiver. The third interconnect is a secondary processor communication interconnect that relays urgent signals (such as status, interrupt, and reset signals) between the processor and the radio transceiver's microcontroller. A received signal strength indicator interconnect is the fourth interconnect and it relays an analog signal specifying the strength of an incoming signal from the radio to the computer system. The fifth interconnect is a power supply link for supplying power signals to the radio transceiver. Finally, the sixth interconnect is a half-duplex control interconnect which allows the computer system to control the half-duplex nature of some radio transceivers.
摘要翻译：一种用于计算机系统的处理器的方法和装置，用于通过具有六个互连的总线接口来控制通信设备。总线接口的第一互连是允许计算机系统从通信设备（例如电话线路或无线电收发机）发送和接收信号的发送和接收互连。第二互连是主处理器通信互连，其用作处理器和无线电收发器的微控制器之间的主要通信路由，并且其使得处理器能够控制无线电收发器的各种组件。第三互连是二级处理器通信互连，其中继处理器和无线电收发器的微控制器之间的紧急信号（例如状态，中断和复位信号）。接收到的信号强度指示器互连是第四互连，并且它中继一个模拟信号，指定从无线电到计算机系统的输入信号的强度。第五互连是用于向无线电收发器提供电力信号的电源链路。最后，第六个互连是半双工控制互连，允许计算机系统控制一些无线电收发器的半双工性质。

10. 发明申请

US20060090040A1 Techniques to improve cache performance 有权
标题翻译：提高缓存性能的技术
公开(公告)号：US20060090040A1
公开(公告)日：2006-04-27
申请号：US10973793
申请日：2004-10-25
申请人： Michael Eschmann
发明人： Michael Eschmann
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0866
摘要： Method and apparatus to improve cache performance using interarrival times between demand requests are described.
摘要翻译：描述了在需求请求之间使用差异时间来提高高速缓存性能的方法和装置。

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