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1. 发明授权

US07554908B2 Techniques to manage flow control 有权
标题翻译：管理流量控制的技术
公开(公告)号：US07554908B2
公开(公告)日：2009-06-30
申请号：US11009861
申请日：2004-12-10
申请人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert Wolrich , Hugh M. Wilkinson
发明人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert Wolrich , Hugh M. Wilkinson
IPC分类号： G06F11/00 , H04J3/14 , H04L12/26
CPC分类号： H04L47/10 , H04L49/15 , H04L49/254 , H04L49/30 , H04L2012/5678
摘要： Method and apparatus to manage flow control for a network device are described.
摘要翻译：描述了一种用于管理网络设备的流量控制的方法和装置。

2. 发明申请

US20090119671A1 REGISTERS FOR DATA TRANSFERS 审中-公开
标题翻译：数据传输寄存器
公开(公告)号：US20090119671A1
公开(公告)日：2009-05-07
申请号：US12249786
申请日：2008-10-10
申请人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
发明人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
IPC分类号： G06F9/46 , G06F9/44 , G06F15/00 , G06F9/30 , G06F12/00
CPC分类号： G06F9/4843 , G06F9/30101 , G06F9/3012 , G06F9/30123 , G06F9/3851
摘要： A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.
摘要翻译：一种用于在多个硬件上下文和编程引擎中采用用于数据传输的寄存器以便于高性能数据处理的系统和方法。该系统和方法包括处理器，其包括具有寄存器的编程引擎，用于将驻留在执行编程引擎中的寄存器中的一个寄存器中的数据传送到驻留在相邻编程引擎中的后续寄存器中的寄存器。

3. 发明授权

US07443836B2 Processing a data packet 有权
标题翻译：处理数据包
公开(公告)号：US07443836B2
公开(公告)日：2008-10-28
申请号：US10463217
申请日：2003-06-16
申请人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
发明人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
IPC分类号： H04L12/66
CPC分类号： G06F9/3851 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9057 , H04L49/9094
摘要： A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.
摘要翻译：描述用于在设备处理数据分组的设备和方法。设备接收数据分组并且确定多个执行线程的一个或多个本地存储器中的可用存储器。该设备将分组信息存储在执行线程的本地存储器中的可用的一个中。

4. 发明授权

US06934951B2 Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section 有权
标题翻译：并行处理器，功能管道提供编程引擎，支持多个上下文和关键部分
公开(公告)号：US06934951B2
公开(公告)日：2005-08-23
申请号：US10053172
申请日：2002-01-17
申请人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
发明人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
IPC分类号： G06F15/78 , G06F9/46
CPC分类号： G06F15/8053
摘要： A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.
摘要翻译：一种用于在功能管线中采用多个硬件上下文和编程引擎的系统和方法，该功能管线被划分以便于高性能数据处理。该系统和方法包括并行处理器，其分配用于处理数据的系统功能，所述系统功能包括支持多个上下文的编程引擎，所述编程引擎被布置为通过在所述编程引擎之间传递功能数据的功能流水线控制单元提供功能

5. 发明授权

US07437724B2 Registers for data transfers 有权
标题翻译：注册数据传输
公开(公告)号：US07437724B2
公开(公告)日：2008-10-14
申请号：US10116670
申请日：2002-04-03
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta , Hugh M. Wilkinson, III
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta , Hugh M. Wilkinson, III
IPC分类号： G06F9/46 , G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/4843 , G06F9/30101 , G06F9/3012 , G06F9/30123 , G06F9/3851
摘要： A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.
摘要翻译：一种用于在多个硬件上下文和编程引擎中采用用于数据传输的寄存器以便于高性能数据处理的系统和方法。该系统和方法包括处理器，其包括具有寄存器的编程引擎，用于将驻留在执行编程引擎中的寄存器中的一个寄存器中的数据传送到驻留在相邻编程引擎中的后续寄存器中的寄存器。

6. 发明授权

US07302549B2 Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access 有权
标题翻译：处理使用相同功能的数据包序列设置流水线多个线程跨越多个处理引擎并具有独占数据访问
公开(公告)号：US07302549B2
公开(公告)日：2007-11-27
申请号：US11092366
申请日：2005-03-29
申请人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
发明人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
IPC分类号： G06F9/46
CPC分类号： G06F15/8053
摘要： A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning multiple programmable processing elements integrated within a processor, and with the programmable processing elements providing multiple threads of execution such that each of the threads acquires exclusive modification access to data shared.
摘要翻译：一种用于在功能管线中采用多个硬件上下文和编程引擎的系统和方法，该功能管线被划分以便于高性能数据处理。该系统和方法包括用线程序列处理一系列分组，其中线程序列跨越集成在处理器内的多个可编程处理元件，并且可编程处理元件提供多个执行线程，使得每个线程获得排他性修改访问数据共享。

7. 发明授权

US07181594B2 Context pipelines 有权
标题翻译：上下文管道
公开(公告)号：US07181594B2
公开(公告)日：2007-02-20
申请号：US10057723
申请日：2002-01-25
申请人： Hugh M. Wilkinson, III , Mark B. Rosenbluth , Matthew J. Adiletta , Debra Bernstein , Gilbert Wolrich
发明人： Hugh M. Wilkinson, III , Mark B. Rosenbluth , Matthew J. Adiletta , Debra Bernstein , Gilbert Wolrich
IPC分类号： G06F9/312
CPC分类号： G06F9/462 , G06F9/30123
摘要： A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.
摘要翻译：描述了一种基于并行硬件的多线程处理方法。该方法包括将分组处理的任务分配给编程引擎，并在与编程引擎相对应的编程阶段之间建立管线。该方法还包括为编程引擎上分配的任务建立上下文，并使用诸如CAM的软件控制的高速缓存来在驻留在编程引擎中的下一个相邻寄存器之间传送数据。

8. 发明授权

US07325099B2 Method and apparatus to enable DRAM to support low-latency access via vertical caching 失效
标题翻译：使DRAM能够通过垂直高速缓存支持低延迟访问的方法和装置
公开(公告)号：US07325099B2
公开(公告)日：2008-01-29
申请号：US10974122
申请日：2004-10-27
申请人： Sanjeev Jain , Mark B. Rosenbluth , Matthew Adiletta , Gilbert Wolrich
发明人： Sanjeev Jain , Mark B. Rosenbluth , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： H04L12/2854 , G06F12/0862 , G06F12/0875
摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.
摘要翻译：实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。在一个实施例中，DRAM包括双数据速率（DDR）DRAM。公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。该架构还包括用于执行各种分组处理功能的多个计算引擎。一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。随后，一个或多个分组处理功能可以通过从高速缓存访问功能元数据来操作。功能完成后，将功能元数据写回到基于DRAM的商店。该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

9. 发明授权

US07251219B2 Method and apparatus to communicate flow control information in a duplex network processor system 有权
标题翻译：在双工网络处理器系统中传送流量控制信息的方法和装置
公开(公告)号：US07251219B2
公开(公告)日：2007-07-31
申请号：US10188081
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Yim Pun , Raymond Ng , Hugh M. Wilkinson, III , Mark B. Rosenbluth , David Romano
发明人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Yim Pun , Raymond Ng , Hugh M. Wilkinson, III , Mark B. Rosenbluth , David Romano
IPC分类号： H04B1/44
CPC分类号： H04L49/30 , H04L47/10 , H04L47/266 , H04L47/30 , H04L49/254 , H04L49/50
摘要： In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.
摘要翻译：可以在第一网络处理器处从交换结构接收带内流控制数据。接收到的带内流控制数据可以使用流控制总线发送到第二网络处理器。第二网络处理器可以基于带内流控制数据来确定交换结构中的接收队列超过预定的溢出阈值。第二处理器可以将数据发送到被确定为不超过预定溢出阈值的交换结构中的接收队列。

10. 发明授权

US07324520B2 Method and apparatus to process switch traffic 有权
标题翻译：处理交换机流量的方法和装置
公开(公告)号：US07324520B2
公开(公告)日：2008-01-29
申请号：US10188419
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047 , H04L49/9073
摘要： A system and method for reassembling c-frames into coherent packets are disclosed. C-frames contain segments of a data set. A micro-engine operating multiple threads copies the data set segments into assigned queues, following a thread hierarchy to keep the segments in order. The queues are stored in SRAM. The micro-engine maintains a subset of the total number of queues in local memory. If a segment belongs to a queue not in local memory, the least recently used queue is copied to SRAM, the required queue is read from SRAM, and the queue is updated with the data set segment.
摘要翻译：公开了一种用于将c帧重新组合成相干分组的系统和方法。 C帧包含数据集的段。运行多个线程的微引擎将数据集段复制到分配的队列中，遵循线程层次结构以保持段的顺序。队列存储在SRAM中。微引擎维护本地内存中队列总数的一个子集。如果段属于不在本地存储器中的队列，则将最近最少使用的队列复制到SRAM，从SRAM读取所需的队列，并且使用数据集段更新队列。

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