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1. 发明申请

US20120232950A1 SPEND ANALYSIS SYSTEM AND METHOD 审中-公开
标题翻译： SPEND分析系统和方法
公开(公告)号：US20120232950A1
公开(公告)日：2012-09-13
申请号：US13113034
申请日：2011-05-21
申请人： Sanjay Kadkol , Bikash Mohanty , Ashish Jha , Aloysius Sebastian
发明人： Sanjay Kadkol , Bikash Mohanty , Ashish Jha , Aloysius Sebastian
IPC分类号： G06Q10/00
CPC分类号： G06Q10/063 , G06Q10/0639 , G06Q10/067
摘要： System and method for spend analysis are provided. The method includes identifying a spend category and associating a cost component model to the spend category. The cost component model indicates one or more cost contributors to the spend category. The method also includes receiving market information associated with at least a subset of the one or more cost contributors in the cost component model and outputting an analysis of spend associated with the spend category in relation to the cost component model.
摘要翻译：提供了花费分析的系统和方法。该方法包括识别支出类别并将成本组件模型与支出类别相关联。成本组件模型表示支出类别的一个或多个成本贡献者。该方法还包括接收与成本组件模型中的一个或多个成本贡献者的至少一个子集相关联的市场信息，并且输出与花费类别相关联的花费分析与成本组件模型的关系。

2. 发明申请

US20150178752A1 SPEND ANALYSIS SYSTEM AND METHOD 审中-公开
标题翻译： SPEND分析系统和方法
公开(公告)号：US20150178752A1
公开(公告)日：2015-06-25
申请号：US14642056
申请日：2015-03-09
申请人： Sanjay Kadkol , Bikash Mohanty , Ashish Jha , Aloysius Sebastian
发明人： Sanjay Kadkol , Bikash Mohanty , Ashish Jha , Aloysius Sebastian
IPC分类号： G06Q30/02 , G06Q40/00
CPC分类号： G06Q30/0206 , G06Q10/063 , G06Q10/0639 , G06Q10/067 , G06Q40/00
摘要： Systems and methods for a spend analysis are described, and include identifying a spend category and associating a cost component model to the spend category. The cost component model indicates one or more cost contributors to the spend category. The systems and methods also include receiving market information associated with at least a subset of the one or more cost contributors in the cost component model and outputting an analysis of spend associated with the spend category in relation to the cost component model.
摘要翻译：描述支出分析的系统和方法，包括识别支出类别，并将成本组件模型与支出类别相关联。成本组件模型表示支出类别的一个或多个成本贡献者。系统和方法还包括接收与成本组件模型中的一个或多个成本贡献者的至少一个子集相关联的市场信息，并且输出与花费类别相关联的与花费组件模型相关联的支出分析。

3. 发明申请

US20120179586A1 COMPUTER BASED SYSTEM FOR SPEND ANALYSIS SOLUTION THROUGH STRATEGIES FOR MINING SPEND INFORMATION 审中-公开
标题翻译：基于计算机的系统，用于通过采矿活动信息战略的分析解决方案
公开(公告)号：US20120179586A1
公开(公告)日：2012-07-12
申请号：US13423285
申请日：2012-03-19
申请人： Bikash Mohanty , Ashish Jha
发明人： Bikash Mohanty , Ashish Jha
IPC分类号： G06Q40/00
CPC分类号： G06Q10/063 , G06Q40/12
摘要： A computer based system for spend analysis solution through strategies for mining spend information, the system comprises a processor unit; and a computer readable medium storing instructions executable by the processor unit comprising classification means adapted to classify spend data in accordance with pre-determined parameters of classification; categorization means adapted to categorize classified spend data based on pre-defined parameters; input means adapted to input pre-defined fields in relation to category of spend data, supplier information, payment terms, contracts or contract terms, and other pre-defined dimensions; saving strategy analysis engine adapted to analyze classified and categorized spend data based on pre-determined strategies, said saving strategy analysis engine further comprising category based saving strategy analysis engine adapted to output saving strategy per identified category inputs; and supplier based saving strategy analysis engine adapted to output saving strategy per identified supplier inputs.
摘要翻译：一种基于计算机的系统，用于通过采矿支出信息战略的支出分析解决方案，该系统包括一个处理器单元; 以及存储可由所述处理器单元执行的指令的计算机可读介质，所述指令可包括分类装置，所述分类装置适于根据分类的预定参数对支出数据进行分类; 适用于基于预定义参数对分类支出数据进行分类的分类手段; 输入装置适于输入关于花费数据类别，供应商信息，付款条件，合同或合同条款以及其他预定义维度的预定义字段; 所述保存策略分析引擎还包括基于类别的保存策略分析引擎，所述引擎适于根据所识别的类别输入输出保存策略; 和基于供应商的储蓄策略分析引擎，适用于根据确定的供应商输入输出储蓄策略。

4. 发明申请

US20140011726A1 LOW-VOC CLEANING SUBSTRATES AND COMPOSITIONS COMPRISING A CATIONIC BIOCIDE 有权
标题翻译：低VOC清洁基材和包含阳离子生物体的组合物
公开(公告)号：US20140011726A1
公开(公告)日：2014-01-09
申请号：US13543232
申请日：2012-07-06
申请人： Diana Mitchell , Sarah Coulter , Ashish Jha , William Ouellette , Gregory Van Buskirk
发明人： Diana Mitchell , Sarah Coulter , Ashish Jha , William Ouellette , Gregory Van Buskirk
IPC分类号： C11D3/48
CPC分类号： C11D3/48 , A01N33/12 , A47L13/17 , C11D1/008 , C11D1/62 , C11D1/66 , C11D1/72 , C11D1/835 , C11D3/43
摘要： A cleaning composition for sanitizing and/or disinfecting hard surfaces, comprising: a cationic biocide, surfactant and low levels of VOC solvents. The cleaning composition is adapted to clean a variety of hard surfaces without leaving behind a visible residue and creates low levels of streaking and filming on the treated surface. The cleaning composition contains less than 5% by weight of VOCs. The cleaning composition may be used alone as a liquid or spray formulation or in combination with a substrate, for example, a pre-loaded cleaning wipe.
摘要翻译：一种用于消毒和/或消毒硬表面的清洁组合物，包括：阳离子杀生物剂，表面活性剂和低水平的VOC溶剂。清洁组合物适于清洁各种硬表面，而不会留下可见的残留物，并在经处理的表面上产生低水平的条纹和成膜。清洁组合物含有小于5重量％的VOC。清洁组合物可以单独用作液体或喷雾制剂，或与基底组合使用，例如预先装载的清洁擦拭巾。

5. 发明授权

US10055225B2 Multi-register scatter instruction 有权
公开(公告)号：US10055225B2
公开(公告)日：2018-08-21
申请号：US13995433
申请日：2011-12-23
申请人： Ashish Jha
发明人： Ashish Jha
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30032 , G06F9/30036
摘要： A processor fetches a multi-register scatter instruction that includes a source operand and a destination operand. The source operand specifies a source vector register that includes multiple source data elements. The destination operand identifies multiple destination data elements that each specify a destination vector register and an index into that destination vector register. The instruction is decoded and executed, causing, for each of those identified destination data elements, the one of the source data elements that is in a position in the source vector register that corresponds with a position of that destination data element to be stored in the destination vector register at the index specified by that destination data element.

6. 发明授权

US09766887B2 Multi-register gather instruction 有权
公开(公告)号：US09766887B2
公开(公告)日：2017-09-19
申请号：US13995437
申请日：2011-12-23
申请人： Ashish Jha
发明人： Ashish Jha
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032
摘要： A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand that identifies content that indicates multiple vector registers, a first set of indexes of each of the vector registers that each identifies a source data element, and a second set of indexes of the destination vector register for each identified source element. The instruction is decoded and executed, causing, for each of the first set of indexes of each of the vector registers, the source data element that corresponds to that index of that vector register to be stored in a set of destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.

7. 发明申请

US20170192781A1 Systems, Apparatuses, and Methods for Strided Loads 审中-公开
公开(公告)号：US20170192781A1
公开(公告)日：2017-07-06
申请号：US14984124
申请日：2015-12-30
申请人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
发明人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/30043 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/30192 , G06F9/3455
摘要： Detailed herein are systems, apparatuses, and methods for strided loads. In an embodiment, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

8. 发明授权

US09348592B2 Apparatus and method for sliding window data access 有权
标题翻译：用于滑动窗口数据访问的装置和方法
公开(公告)号：US09348592B2
公开(公告)日：2016-05-24
申请号：US13995793
申请日：2011-12-22
申请人： Ashish Jha
发明人： Ashish Jha
IPC分类号： G06F13/00 , G06F13/28 , G06F9/30 , G06F9/355 , G06F9/38 , G06F9/44
CPC分类号： G06F9/3013 , G06F8/76 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30047 , G06F9/30127 , G06F9/30145 , G06F9/30185 , G06F9/345 , G06F9/3555 , G06F9/383
摘要： An apparatus and method are described for fetching and storing a plurality of portions of a data stream into a plurality of registers. For example, a method according to one embodiment includes the following operations: determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory; determining the system memory addresses for each of the N designated portions of the data stream; fetching the N designated portions of the data stream from the system memory at the system memory addresses; and storing the N designated portions of the data stream into the N vector registers.
摘要翻译：描述了一种用于将数据流的多个部分取出并存储到多个寄存器中的装置和方法。例如，根据一个实施例的方法包括以下操作：确定一组N个向量寄存器，用于读取存储在系统存储器中的数据流的N个指定部分; 确定数据流的N个指定部分中的每一个的系统存储器地址; 在系统存储器地址处从系统存储器取出数据流的N个指定部分; 并将数据流的N个指定部分存储到N个向量寄存器中。

9. 发明申请

US20170192782A1 Systems, Apparatuses, and Methods for Aggregate Gather and Stride 审中-公开
公开(公告)号：US20170192782A1
公开(公告)日：2017-07-06
申请号：US14984132
申请日：2015-12-30
申请人： Robert Valentine , Mark J. Charney , Elmoustapha Ould-Ahmed-Vall , Ashish Jha
发明人： Robert Valentine , Mark J. Charney , Elmoustapha Ould-Ahmed-Vall , Ashish Jha
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30043 , G06F9/30098 , G06F9/30109 , G06F9/30112
摘要： Embodiments of systems, apparatuses, and methods for aggregate gather and scatter are disclosed. In some embodiments, a decoder to decode an instruction, wherein the instruction to include fields for an index of memory address locations, an immediate, and a starting destination register operand and identifier of additional destination registers; and execution circuitry to execute the decoded instruction to gather, from memory at locations indicated by the index of memory locations, data elements and stores them in multiple destination registers in sizes dictated by the immediate are described.

10. 发明申请

US20140281396A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO CONSOLIDATE UNMASKED ELEMENTS OF OPERATION MASKS 有权
标题翻译：处理器，方法，系统和说明来整合未经处理的操作元件
公开(公告)号：US20140281396A1
公开(公告)日：2014-09-18
申请号：US13842730
申请日：2013-03-15
申请人： Ashish Jha
发明人： Ashish Jha
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30036
摘要： An instruction processing apparatus of an aspect includes a plurality of operation mask registers. The apparatus also includes a decode unit to receive an operation mask consolidation instruction. The operation mask consolidation instruction is to indicate a source operation mask register, of the plurality of operation mask registers, and a destination storage location. The source operation mask register is to include a source operation mask that is to include a plurality of masked elements that are to be disposed within a plurality of unmasked elements. An execution unit is coupled with the decode unit. The execution unit, in response to the operation mask consolidation instruction, is to store a consolidated operation mask in the destination storage location. The consolidated operation mask is to include the unmasked elements from the source operation mask consolidated together. Other apparatus, methods, systems, and instructions are also disclosed.
摘要翻译：一方面的指令处理装置包括多个操作掩码寄存器。该装置还包括用于接收操作掩码合并指令的解码单元。操作掩码合并指令是指示多个操作掩码寄存器中的源操作掩码寄存器和目的地存储位置。源操作屏蔽寄存器包括源操作掩码，该源操作掩码将包括要被布置在多个未屏蔽元件内的多个屏蔽元件。执行单元与解码单元耦合。执行单元响应于操作掩码合并指令，将合并的操作掩码存储在目的地存储位置中。合并操作掩码是将来自源操作掩码的未屏蔽元素合并在一起。还公开了其他装置，方法，系统和指令。

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