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1. 发明申请

US20090242961A1 RECESSED CHANNEL SELECT GATE FOR A MEMORY DEVICE 审中-公开
标题翻译：记忆体设备的通道选通门
公开(公告)号：US20090242961A1
公开(公告)日：2009-10-01
申请号：US12059024
申请日：2008-03-31
申请人： Sanh Tang , Max Hineman , Kyu Min , Luan Tran
发明人： Sanh Tang , Max Hineman , Kyu Min , Luan Tran
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568
摘要： A memory device comprising one or more recessed channel select gates and at least one charge trapping layer.
摘要翻译：一种存储器件，包括一个或多个凹陷沟道选择栅极和至少一个电荷俘获层。

2. 发明申请

US20070141771A1 Integrated circuits and methods of forming a field effect transistor 有权
公开(公告)号：US20070141771A1
公开(公告)日：2007-06-21
申请号：US11704487
申请日：2007-02-09
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L21/8238
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

3. 发明申请

US20070020819A1 Vertical transistor structures having vertical-surrounding-gates with self-aligned features 有权
公开(公告)号：US20070020819A1
公开(公告)日：2007-01-25
申请号：US11495473
申请日：2006-07-28
申请人： Sanh Tang , Grant Huglin
发明人： Sanh Tang , Grant Huglin
IPC分类号： H01L21/332 , H01L21/84 , H01L21/338 , H01L21/337 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/42392 , H01L29/66666 , H01L29/7827
摘要： The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.

4. 发明申请

US20060261393A1 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors 有权
公开(公告)号：US20060261393A1
公开(公告)日：2006-11-23
申请号：US11496930
申请日：2006-07-31
申请人： Sanh Tang , Gordon Haller , Kris Brown , Tuman Earl Allen
发明人： Sanh Tang , Gordon Haller , Kris Brown , Tuman Earl Allen
IPC分类号： H01L29/94
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

5. 发明申请

US20060205128A1 Integrated circuits and methods of forming a field effect transistor 有权
标题翻译：集成电路和形成场效应晶体管的方法
公开(公告)号：US20060205128A1
公开(公告)日：2006-09-14
申请号：US11076774
申请日：2005-03-10
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L21/8234 , H01L21/76 , H01L21/20
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
摘要翻译：公开了形成场效应晶体管的集成电路和方法。在一个方面，集成电路包括包括本体半导体材料的半导体衬底。电绝缘材料容纳在本体半导体材料内。在绝缘材料上形成半导体材料。包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。公开了其他方面和实施方式，包括方法方面。

6. 发明申请

US20060043471A1 Vertical transistor structures having vertical-surrounding-gates with self-aligned features 有权
标题翻译：垂直晶体管结构具有具有自对准特征的垂直环形栅极
公开(公告)号：US20060043471A1
公开(公告)日：2006-03-02
申请号：US10928522
申请日：2004-08-26
申请人： Sanh Tang , Grant Huglin
发明人： Sanh Tang , Grant Huglin
IPC分类号： H01L29/76
CPC分类号： H01L29/42392 , H01L29/66666 , H01L29/7827
摘要： The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.
摘要翻译：本发明包括通过定义具有自对准特征的垂直环绕栅极场效应晶体管的沟道长度而形成的垂直晶体管。该方法提供了定义晶体管沟道长度的工艺步骤和用于形成用于制造半导体器件的垂直周围栅极场效应晶体管结构的凹槽硅柱。

7. 发明申请

US20060043449A1 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors 有权
标题翻译：半导体结构和晶体管，以及形成半导体结构和晶体管的方法
公开(公告)号：US20060043449A1
公开(公告)日：2006-03-02
申请号：US10932150
申请日：2004-09-01
申请人： Sanh Tang , Gordon Haller , Kris Brown , Tuman Allen
发明人： Sanh Tang , Gordon Haller , Kris Brown , Tuman Allen
IPC分类号： H01L29/94
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
摘要翻译：本发明包括具有上表面的半导体衬底的晶体管器件。一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。栅极形成在半导体衬底中的一对源/漏区之间。

8. 发明授权

US6162721A Semiconductor processing methods 失效
标题翻译：半导体加工方法
公开(公告)号：US6162721A
公开(公告)日：2000-12-19
申请号：US183486
申请日：1998-10-30
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768 , H01L21/822 , H01L23/485 , H01L27/04 , H01L29/417 , H01L21/44
CPC分类号： H01L29/417 , H01L21/76885 , H01L23/485 , H01L2924/0002 , Y10S257/903 , Y10S438/97 , H01L2924/00
摘要： A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which connects with the base region through the second layer plug; and h) etching unmasked portions of the first layer and second layer plug to define a circuit component which connects with the base region through the second layer plug, the greater thickness of the second layer plug as compared to the thickness of the first layer restricting etching into the base region during etching. Integrated circuitry is also disclosed.
摘要翻译：半导体处理方法包括：a）提供具有要与其进行电连接的基极区域的基板; b）提供第一层导电第一材料; c）在第一层上提供蚀刻停止层; d）通过蚀刻停止层和第一层蚀刻到基底区域的接触开口; e）在所述蚀刻停止层的外部和所述接触开口内提供第二层第一材料，其厚度大于所述第一层厚度并向外延伸超出所述接触开口上边缘; f）去除第二层的第一材料并在接触件内限定第二层塞，第二层塞具有向外延伸超过接触开口上边缘的最外表面，从而使第二层塞具有比第一层层; g）从第一层和第二层插塞向外掩蔽，以限定掩模图案，用于定义来自第一层的电路部件，该第一层通过第二层插塞与基部区域连接; 以及h）蚀刻所述第一层和第二层插塞的未屏蔽部分以限定通过所述第二层插塞与所述基底区域连接的电路部件，所述第二层插塞的厚度与所述第一层限制蚀刻的厚度相比较大在蚀刻期间进入基底区域。还公开了集成电路。

9. 发明授权

US6160296A Titanium nitride interconnects 有权
标题翻译：氮化钛互连
公开(公告)号：US6160296A
公开(公告)日：2000-12-12
申请号：US338211
申请日：1999-06-22
申请人： Michael P. Violette , Sanh Tang , Daniel M. Smith
发明人： Michael P. Violette , Sanh Tang , Daniel M. Smith
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L29/76 , H01L23/48 , H01L29/94
CPC分类号： H01L21/76855 , H01L21/32053 , H01L21/32137 , H01L21/76843 , H01L21/76846 , H01L21/76895
摘要： A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.
摘要翻译：用于制造半导体器件的方法包括在氮化钛膜上形成氮化钛膜并沉积硅硬掩模。硅硬掩模用于从氮化钛膜图案化氮化钛互连，并且硅硬掩模也用作用于形成接触区域的接触蚀刻停止。在形成互连件时，将硅硬掩模干蚀刻选择性地停止并暴露氮化钛膜的部分，并且氮化钛膜的暴露部分被蚀刻，导致氮化钛互连。在使用硅硬掩模作为接触蚀刻停止件时，在硅硬掩模上沉积绝缘层，并且使用硅硬掩模作为蚀刻停止层来蚀刻绝缘层以形成接触区域。然后将硅硬掩模转换成金属硅化物接触区域。还描述了使用该方法形成的互连。

10. 发明授权

US07989336B2 Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry 有权
标题翻译：在集成电路的制造中形成多条导线的方法，形成导线阵列的方法和集成电路
公开(公告)号：US07989336B2
公开(公告)日：2011-08-02
申请号：US12436262
申请日：2009-05-06
申请人： Sanh Tang , Ming Zhang
发明人： Sanh Tang , Ming Zhang
IPC分类号： H01L21/4763 , H01L21/76 , H01L21/336
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76838 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.
摘要翻译：在集成电路的制造中形成一对导线的方法包括将沟槽形成为接纳在衬底上的镶嵌材料。导电材料沉积在镶嵌材料上并且在沟槽内沉积以覆盖沟槽。导电材料至少被去除到镶嵌材料，以留下留在沟槽中的至少一些导电材料。蚀刻通过沟槽内的导电材料纵向导电，以在沟槽内形成第一和第二导电线，该沟槽中的第一和第二导电线沿着第一和第二导电线的至少大部分长度在横截面上相互镜像。考虑其他实现。

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