专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08120101B2 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors 有权
标题翻译：半导体结构和晶体管，以及形成半导体结构和晶体管的方法
公开(公告)号：US08120101B2
公开(公告)日：2012-02-21
申请号：US12891407
申请日：2010-09-27
申请人： Sanh D. Tang , Gordon A. Haller , Kris K. Brown , Tuman Earl Allen, III
发明人： Sanh D. Tang , Gordon A. Haller , Kris K. Brown , Tuman Earl Allen, III
IPC分类号： H01L29/76
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
摘要翻译：本发明包括具有上表面的半导体衬底的晶体管器件。一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。栅极形成在半导体衬底中的一对源/漏区之间。

2. 发明授权

US07825462B2 Transistors 有权
标题翻译：晶体管
公开(公告)号：US07825462B2
公开(公告)日：2010-11-02
申请号：US12070078
申请日：2008-02-15
申请人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen, III
发明人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen, III
IPC分类号： H01L29/76
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
摘要翻译：本发明包括具有上表面的半导体衬底的晶体管器件。一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。栅极形成在半导体衬底中的一对源/漏区之间。

3. 发明授权

US07547945B2 Transistor devices, transistor structures and semiconductor constructions 有权
标题翻译：晶体管器件，晶体管结构和半导体结构
公开(公告)号：US07547945B2
公开(公告)日：2009-06-16
申请号：US10932150
申请日：2004-09-01
申请人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen, III
发明人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen, III
IPC分类号： H01L29/76
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
摘要翻译：本发明包括具有上表面的半导体衬底的晶体管器件。一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。栅极形成在半导体衬底中的一对源/漏区之间。

4. 发明授权

US07501684B2 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07501684B2
公开(公告)日：2009-03-10
申请号：US11496930
申请日：2006-07-31
申请人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen, III
发明人： Sanh D. Tang , Gordon Haller , Kris K. Brown , Tuman Earl Allen, III
IPC分类号： H01L29/76
CPC分类号： H01L29/41758 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/66621 , H01L29/78
摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.
摘要翻译：本发明包括具有上表面的半导体衬底的晶体管器件。一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。栅极形成在半导体衬底中的一对源/漏区之间。

5. 发明授权

US06478978B1 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 失效
标题翻译：蚀刻方法，去除部分材料的方法以及形成氮化硅间隔物的方法
公开(公告)号：US06478978B1
公开(公告)日：2002-11-12
申请号：US09516638
申请日：2000-03-01
申请人： Tuman Earl Allen, III
发明人： Tuman Earl Allen, III
IPC分类号： H01L2170
CPC分类号： H01L21/31116 , Y10S438/905
摘要： The invention includes a method of patterning a material over a semiconductive substrate, comprising: a) forming a layer of first material against a second material and over the substrate, the semiconductive substrate comprising a surface having a center and an edge; b) first etching the first material in a reaction chamber, the first etching comprising a first center-to-edge uniformity across the surface of the wafer and comprising a first selectivity for the first material relative to the second material; c) second etching the first material in the reaction chamber, the second etching comprising a second selectivity for the first material relative to the second material, the second center-to-edge uniformity being less than the first center-to-edge uniformity, the second selectivity being greater than the first selectivity; and d) cleaning a component of the first material from at least one sidewall of the reaction chamber between the first and second etchings.
摘要翻译：本发明包括一种在半导体衬底上图案化材料的方法，包括：a）在第二材料上和衬底上形成第一材料层，所述衬底包括具有中心和边缘的表面; b）首先在反应室中蚀刻第一材料，第一蚀刻包括横跨晶片表面的第一中心到边缘的均匀性，并且包括第一材料相对于第二材料的第一选择性; c）第二蚀刻反应室中的第一材料，第二蚀刻包括相对于第二材料的第一材料的第二选择性，第二中心对边缘均匀性小于第一中心到边缘的均匀性，第二选择性大于第一选择性; 以及d）在所述第一和第二蚀刻之间从所述反应室的至少一个侧壁清洁所述第一材料的部件。

6. 发明授权

US06878300B2 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 失效
标题翻译：去除材料的方法
公开(公告)号：US06878300B2
公开(公告)日：2005-04-12
申请号：US10262727
申请日：2002-10-01
申请人： Tuman Earl Allen, III
发明人： Tuman Earl Allen, III
IPC分类号： H01L21/311 , H01L21/00
CPC分类号： H01L21/31116 , Y10S438/905
摘要： In one embodiment, the invention includes a method of removing at least a portion of a material from a substrate. The method includes providing a substrate in a reaction chamber, the substrate having a material supported thereover, and first etching the material while the substrate is in the reaction chamber. The method also includes, after the first etching, cleaning a component from at least one sidewall of the reaction chamber while the substrate remains therein; the component comprising a species that is present in the material. The cleaning includes exposing the sidewall and substrate to conditions which substantially selectively remove the component from the sidewall while not removing the material from the substrate, and not etching any other materials supported by the substrate. After the cleaning, the method includes second etching the material while the substrate is in the reaction chamber.
摘要翻译：在一个实施例中，本发明包括从衬底去除材料的至少一部分的方法。该方法包括在反应室中提供衬底，该衬底具有支撑在其上的材料，并且在衬底位于反应室中时首先蚀刻该材料。该方法还包括在第一蚀刻之后，当基板保持在其中时，从反应室的至少一个侧壁清洁部件; 所述组分包含存在于所述材料中的物质。清洁包括将侧壁和基底暴露于基本上选择性地从侧壁移除部件而不从基板移除材料并且不蚀刻由基板支撑的任何其它材料的条件。在清洁之后，该方法包括在衬底处于反应室中时第二次蚀刻材料。

7. 发明授权

US06479393B1 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 失效
标题翻译：蚀刻方法，去除部分材料的方法以及形成氮化硅间隔物的方法
公开(公告)号：US06479393B1
公开(公告)日：2002-11-12
申请号：US09516635
申请日：2000-03-01
申请人： Tuman Earl Allen, III
发明人： Tuman Earl Allen, III
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , Y10S438/905
摘要： A processing method includes patterning a material over a semiconductive substrate having a center and an edge. The method includes forming a layer of first material against a second material and over the semiconductive substrate and first etching the first material in a reaction chamber. First etching provides a first center-to-edge uniformity across the wafer surface and a first selectivity for the first material relative to the second material. The method also includes second etching the first material to provide a second center-to-edge uniformity across the wafer surface and a second selectivity greater than the first selectivity for the first material relative to the second material. The second center-to-edge uniformity is less than the first center-to-edge uniformity. The method also includes cleaning a component of the first material from at least one sidewall of the reaction chamber between the first and second etchings.
摘要翻译：一种处理方法包括在具有中心和边缘的半导体衬底上图案化材料。该方法包括在第二材料上并在半导体衬底上形成第一材料层，并首先在反应室中蚀刻第一材料。第一蚀刻提供跨晶片表面的第一中心到边缘均匀性，并且相对于第二材料提供第一材料的第一选择性。该方法还包括第二蚀刻第一材料以在晶片表面上提供第二中心到边缘均匀性，第二选择性大于第一材料相对于第二材料的第一选择性。第二中心到边缘均匀性小于第一中心到边缘的均匀性。该方法还包括从第一和第二蚀刻之间的反应室的至少一个侧壁清洗第一材料的组分。

8. 发明授权

US06800561B2 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 失效
标题翻译：蚀刻方法，去除部分材料的方法以及形成氮化硅间隔物的方法
公开(公告)号：US06800561B2
公开(公告)日：2004-10-05
申请号：US10261549
申请日：2002-09-30
申请人： Tuman Earl Allen, III
发明人： Tuman Earl Allen, III
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , Y10S438/905
摘要： A processing method includes patterning a material over a semiconductive substrate having a center and an edge. The method includes forming a layer of first material against a second material and over the semiconductive substrate and first etching the first material in a reaction chamber. First etching provides a first center-to-edge uniformity across the wafer surface and a first selectivity for the first material relative to the second material. The method also includes second etching the first material to provide a second center-to-edge uniformity across the wafer surface and a second selectivity greater than the first selectivity for the first material relative to the second material. The second center-to-edge uniformity is less than the first center-to-edge uniformity. The method also includes cleaning a component of the first material from at least one sidewall of the reaction chamber between the first and second etchings.
摘要翻译：一种处理方法包括在具有中心和边缘的半导体衬底上图案化材料。该方法包括在第二材料上并在半导体衬底上形成第一材料层，并首先在反应室中蚀刻第一材料。第一蚀刻提供跨晶片表面的第一中心到边缘均匀性，并且相对于第二材料提供第一材料的第一选择性。该方法还包括第二蚀刻第一材料以在晶片表面上提供第二中心到边缘均匀性，第二选择性大于第一材料相对于第二材料的第一选择性。第二中心到边缘均匀性小于第一中心到边缘的均匀性。该方法还包括从第一和第二蚀刻之间的反应室的至少一个侧壁清洗第一材料的组分。

9. 发明授权

US06533953B2 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 失效
标题翻译：蚀刻方法，去除部分材料的方法以及形成氮化硅间隔物的方法
公开(公告)号：US06533953B2
公开(公告)日：2003-03-18
申请号：US09797355
申请日：2001-02-28
申请人： Tuman Earl Allen, III
发明人： Tuman Earl Allen, III
IPC分类号： H01L21311
CPC分类号： H01L21/31116 , Y10S438/905
摘要： In one embodiment, the invention includes a method of removing at least a portion of a material from a substrate. The method includes providing a substrate in a reaction chamber, the substrate having a material supported thereover, and first etching the material while the substrate is in the reaction chamber. The method also includes, after the first etching, cleaning a component from at least one sidewall of the reaction chamber while the substrate remains therein; the component comprising a species that is present in the material. The cleaning includes exposing the sidewall and substrate to conditions which substantially selectively remove the component from the sidewall while not removing the material from the substrate, and not etching any other materials supported by the substrate. After the cleaning, the method includes second etching the material while the substrate is in the reaction chamber.
摘要翻译：在一个实施例中，本发明包括从衬底去除材料的至少一部分的方法。该方法包括在反应室中提供衬底，该衬底具有支撑在其上的材料，并且在衬底位于反应室中时首先蚀刻该材料。该方法还包括在第一蚀刻之后，当基板保持在其中时，从反应室的至少一个侧壁清洁部件; 所述组分包含存在于所述材料中的物质。清洁包括将侧壁和基底暴露于基本上选择性地从侧壁移除部件而不从基板移除材料并且不蚀刻由基板支撑的任何其它材料的条件。在清洁之后，该方法包括在衬底处于反应室中时第二次蚀刻材料。

10. 发明授权

US06235213B1 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers 失效
标题翻译：蚀刻方法，去除部分材料的方法以及形成氮化硅间隔物的方法
公开(公告)号：US06235213B1
公开(公告)日：2001-05-22
申请号：US09080656
申请日：1998-05-18
申请人： Tuman Earl Allen, III
发明人： Tuman Earl Allen, III
IPC分类号： B44C122
CPC分类号： H01L21/31116 , Y10S438/905
摘要： In one aspect, the invention includes a method of removing at least a portion of a material from a substrate, comprising: a) first etching the material in a reaction chamber; b) second etching the material in the reaction chamber; and c) cleaning a component of the material from at least one sidewall of the reaction chamber between the first etching and the second etching. In another aspect, the invention includes a method of patterning a material over a semiconductive substrate, comprising: a) forming a layer of first material against a second material and over a semiconductive substrate, the semiconductive substrate comprising a surface having a center and an edge; b) first etching the first material in a reaction chamber, the first etching comprising a first center-to-edge uniformity across the surface of the wafer and comprising a first selectivity for the first material relative to the second material; c) second etching the first material in the reaction chamber, the second etching comprising a second center-to-edge uniformity across the surface of the wafer and comprising a second selectivity for the first material relative to the second material, the second center-to-edge uniformity being less than the first center-to-edge uniformity, the second selectivity being greater than the first selectivity; and d) cleaning a component of the first material from at least one sidewall of the reaction chamber between the first etching and the second etching.
摘要翻译：在一个方面，本发明包括从衬底去除材料的至少一部分的方法，包括：a）首先在反应室中蚀刻所述材料; b）第二次蚀刻反应室中的材料; 以及c）在所述第一蚀刻和所述第二蚀刻之间，从所述反应室的至少一个侧壁清洁所述材料的成分。在另一方面，本发明包括一种在半导体衬底上图案化材料的方法，包括：a）形成第一材料层以抵抗第二材料并在半导电衬底上，所述半导体衬底包括具有中心和边缘的表面 ; b）首先在反应室中蚀刻第一材料，第一蚀刻包括横跨晶片表面的第一中心到边缘的均匀性，并且包括第一材料相对于第二材料的第一选择性; c）第二蚀刻所述反应室中的第一材料，所述第二蚀刻包括穿过所述晶片表面的第二中心至边缘均匀性，并且包括所述第一材料相对于所述第二材料的第二选择性，所述第二中心至 - 均匀性小于第一中心对边缘均匀性，第二选择性大于第一选择性; 以及d）在所述第一蚀刻和所述第二蚀刻之间，从所述反应室的至少一个侧壁清洁所述第一材料的成分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式