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    • 2. 发明授权
    • EPROM cell using trench isolation to provide leak current immunity
    • EPROM单元采用沟槽隔离提供漏电流抗扰度
    • US5223731A
    • 1993-06-29
    • US804478
    • 1991-12-09
    • Sangsoo Lee
    • Sangsoo Lee
    • H01L21/28H01L21/336H01L27/115H01L29/06H01L29/788
    • H01L29/66825H01L21/28273H01L27/115H01L29/0653H01L29/7886
    • Disclosed is a floating gate EPROM cell wherein a trench is formed in and divides the semiconductor substrate into two portions. Separated source and drain regions are formed in one portion and contact one side of the trench region, and a control gate region is formed in the second portion and contacts the opposite side of the trench. A first insulating film covers the source, drain, trench regions and part of the control gate region, a portion of which is covered by a first polycrystalline silicon film which forms the floating gate. A second insulating layer covers the first polycrystalline silicon film and also a portion of the control gate region, which, in turn, is covered by a second polycrystalline silicon layer which extends beyond the second insulating layer into electrical contact with the control gate region. Thus, a control gate is provided both above and below the floating gate. The coupling efficiency between the control gate and the floating gate is primarily determined by the thickness of the first insulating film, which allows the second insulating film to be thicker to insure against current leakage from the floating gate and at the same time easier to deposit.
    • 公开了一种浮栅EPROM单元,其中沟槽形成在半导体衬底中并分成两部分。 分离的源极和漏极区域形成在一个部分中并且接触沟槽区域的一侧,并且控制栅极区域形成在第二部分中并且接触沟槽的相对侧。 第一绝缘膜覆盖源极,漏极,沟槽区域和控制栅极区域的一部分,其一部分由形成浮动栅极的第一多晶硅膜覆盖。 第二绝缘层覆盖第一多晶硅膜以及覆盖控制栅极区域的一部分,其又被延伸超过第二绝缘层的第二多晶硅层覆盖,以与控制栅极区域电接触。 因此,在浮动栅极的上方和下方设置控制栅极。 控制栅极和浮置栅极之间的耦合效率主要由第一绝缘膜的厚度确定,这允许第二绝缘膜更厚以确保来自浮动栅极的电流泄漏,并且同时更容易沉积。
    • 4. 发明授权
    • Method for manufacturing an EPROM cell
    • EPROM单元的制造方法
    • US5296397A
    • 1994-03-22
    • US051621
    • 1993-04-22
    • Sangsoo Lee
    • Sangsoo Lee
    • H01L21/28H01L21/336H01L27/115H01L29/06H01L29/788H01L21/265
    • H01L29/66825H01L21/28273H01L27/115H01L29/0653H01L29/7886
    • Disclosed is a floating gate EPROM cell wherein a trench is formed in and divides the semiconductor substrate into two portions. Separated source and drain regions are formed in one portion and contact one side of the trench region, and a control gate region is formed in the second portion and contacts the opposite side of the trench. A first insulating film covers the source, drain, trench regions and part of the control gate region, a portion of which is covered by a first polycrystalline silicon film which forms the floating gate. A second insulating layer covers the first polycrystalline silicon film and also a portion of the control gate region, which, in turn, is covered by a second polycrystalline silicon layer which extends beyond the second insulating layer into electrical contact with the control gate region. Thus, a control gate is provided both above and below the floating gate. The coupling efficiency between the control gate and the floating gate is primarily determined by the thickness of the first insulating film, which allows the second insulating film to be thicker to insure against current leakage from the floating gate and at the same time easier to deposit.
    • 公开了一种浮栅EPROM单元,其中沟槽形成在半导体衬底中并分成两部分。 分离的源极和漏极区域形成在一个部分中并且接触沟槽区域的一侧,并且控制栅极区域形成在第二部分中并且接触沟槽的相对侧。 第一绝缘膜覆盖源极,漏极,沟槽区域和控制栅极区域的一部分,其一部分由形成浮动栅极的第一多晶硅膜覆盖。 第二绝缘层覆盖第一多晶硅膜以及覆盖控制栅极区域的一部分,其又被延伸超过第二绝缘层的第二多晶硅层覆盖,以与控制栅极区域电接触。 因此,在浮动栅极的上方和下方设置控制栅极。 控制栅极和浮置栅极之间的耦合效率主要由第一绝缘膜的厚度确定,这允许第二绝缘膜更厚以确保来自浮动栅极的电流泄漏,并且同时更容易沉积。