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1. 发明授权

US08559240B2 Sense amplifying circuit, and semiconductor memory device having the same 有权
标题翻译：检测放大电路，以及具有该检测放大电路的半导体存储器件
公开(公告)号：US08559240B2
公开(公告)日：2013-10-15
申请号：US12917602
申请日：2010-11-02
申请人： Sang-Pyo Hong , Doo-Young Kim
发明人： Sang-Pyo Hong , Doo-Young Kim
IPC分类号： G11C16/04
CPC分类号： G11C7/065 , G11C7/02 , G11C7/1048 , G11C2207/005
摘要： A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.
摘要翻译：公开了一种CMOS锁存型读出放大电路。所述电路包括CMOS差分放大器，被配置为放大输入线对的电压信号以产生第一放大电压信号对，并将第一放大电压信号对提供给输出线对，第一预充电电压具有第一电压电平施加到输入线对。电路还包括CMOS锁存型读出放大器，被配置为放大输出线对的电压信号以产生第二放大电压信号对，并将第二放大电压信号对提供给输出线对。电路还包括由第一公共使能信号控制并连接到CMOS差分放大器和CMOS锁存器型读出放大器的第一公共节点，使得第一公共使能信号控制CMOS差分放大器和CMOS锁存器 - 型读出放大器。

2. 发明授权

US07082070B2 Temperature detection circuit and temperature detection method 有权
标题翻译：温度检测电路和温度检测方法
公开(公告)号：US07082070B2
公开(公告)日：2006-07-25
申请号：US10875003
申请日：2004-06-22
申请人： Sang-Pyo Hong
发明人： Sang-Pyo Hong
IPC分类号： G11C7/04 , G11C7/00
CPC分类号： G11C7/04 , G11C5/143 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C29/02 , G11C29/50016 , G11C2029/5002
摘要： A temperature detection circuit and method are provided. The temperature detection circuit samples a first delay time for an input signal at a target temperature to be detected, stores a first addresses generated as the sampled result, samples a second delay time for the input address at a present operating temperature, compares a second addresses generated as the sampled result with the first addresses, and generates a detection signal if the target temperature to be detected is the same as the present operating temperature. The temperature detection method is performed by the temperature detection circuit.
摘要翻译：提供了一种温度检测电路和方法。温度检测电路对要检测的目标温度的输入信号采样第一延迟时间，存储作为采样结果产生的第一地址，对当前工作温度下的输入地址采样第二延迟时间，比较第二地址产生为具有第一地址的采样结果，并且如果要检测的目标温度与当前工作温度相同，则产生检测信号。温度检测方法由温度检测电路进行。

3. 发明授权

US06836311B2 Seal pattern for liquid crystal display device including first, second and third dummy seal patterns in non-active area 有权
标题翻译：液晶显示装置的密封图案包括非活动区域中的第一，第二和第三虚拟密封图案
公开(公告)号：US06836311B2
公开(公告)日：2004-12-28
申请号：US10409571
申请日：2003-04-09
申请人： Sang-Pyo Hong
发明人： Sang-Pyo Hong
IPC分类号： G02F11339
CPC分类号： G02F1/1339
摘要： A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternately in correspondence with the first and second openings.
摘要翻译：用于液晶显示装置的密封图案包括具有有效面积和非有效面积的基底，主密封图案，其具有布置在活性区域和非活性区域之间的边界中的注入孔，以及第一，第二和/ 非活性区域中的第三虚拟密封图案沿着与具有喷射孔的主密封图案的一部分相同的方向布置并彼此间隔开。第一和第二虚拟密封图案具有对应于注入孔的相对端的第一和第二开口。第三虚拟密封图案具有与第一和第二开口相对应地交替设置的第三，第四和第五开口。

4. 发明授权

US07227807B2 Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block 失效
标题翻译：配置存储单元阵列块的方法，寻址方法，半导体存储器件和存储单元阵列块
公开(公告)号：US07227807B2
公开(公告)日：2007-06-05
申请号：US11302606
申请日：2005-12-14
申请人： Sang-Pyo Hong , Du-Yeul Kim
发明人： Sang-Pyo Hong , Du-Yeul Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.
摘要翻译：配置存储单元阵列块的方法包括将第一单元逻辑块划分为子阵列块并将子阵列块的一部分分配给第二单位逻辑块，其中存储单元阵列块对应于子阵列块和第二单元逻辑块，并且子阵列块的部分和第二单元逻辑块共享外围电路。第一单元逻辑块可以基于字线的单位和/或位线的单位被划分为子阵列块。外围电路可以包括行解码器，列解码器，读出放大器和/或均衡/预充电电路。还提供了相关寻址方法，存储单元阵列块和半导体存储器件。

5. 发明申请

US20070109904A1 Memory core and semiconductor memory device having the same 失效
标题翻译：存储器芯和半导体存储器件具有相同的功能
公开(公告)号：US20070109904A1
公开(公告)日：2007-05-17
申请号：US11590313
申请日：2006-10-31
申请人： Sang-Pyo Hong , Jung-Hwa Lee
发明人： Sang-Pyo Hong , Jung-Hwa Lee
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C7/18 , G11C11/4097 , G11C2207/002 , H01L27/10885 , H01L27/10897
摘要： A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column selection circuit including a first column selection transistor and a second column selection transistor, wherein the first and the second selection transistors share a drain and electrically couple the complementary bit line pair to a complementary local input/output line pair, respectively. As a result, the data error due to the distance mismatching can be reduced.
摘要翻译：存储器芯包括包括多个第一存储器单元的第一子存储器阵列，包括多个第二存储单元的第二子存储器阵列，位线放大电路，被配置为放大第一位线和第二存储器单元之间的电压差第二位线和包括第一列选择晶体管和第二列选择晶体管的列选择电路，其中第一和第二选择晶体管共享漏极，并将互补位线对电耦合到互补的本地输入/输出线对，分别。结果，可以减少由于距离不匹配引起的数据错误。

6. 发明授权

US07605409B2 Semiconductor device, method of manufacturing the same, sense amplifier and method of forming the same 有权
标题翻译：半导体器件及其制造方法，感光放大器及其形成方法
公开(公告)号：US07605409B2
公开(公告)日：2009-10-20
申请号：US11673403
申请日：2007-02-09
申请人： Soon-Hong Ahn , Sang-Pyo Hong
发明人： Soon-Hong Ahn , Sang-Pyo Hong
IPC分类号： H01L27/108
CPC分类号： H01L21/823475 , H01L27/0207 , H01L27/10885
摘要： A semiconductor device includes first and second unit circuits. Each first unit circuit has first transistors connected in series, wherein each of the first transistors includes a first gate structure having a pitch. Each second unit circuit has second transistors connected in series, wherein each of the second transistors includes a second gate structure having the pitch. A third transistor and a fourth transistor electrically isolate each of the first and second unit circuits, respectively. An insulation layer covers the first through the fourth transistors. Plugs in the insulation layer are connected to a first gate structure, a second gate structure, a first source region, a first drain region, a second source region or a second drain region. A wiring is connected to the plugs.
摘要翻译：半导体器件包括第一和第二单元电路。每个第一单元电路具有串联连接的第一晶体管，其中每个第一晶体管包括具有间距的第一栅极结构。每个第二单元电路具有串联连接的第二晶体管，其中每个第二晶体管包括具有间距的第二栅极结构。第三晶体管和第四晶体管分别电隔离第一和第二单元电路中的每一个。绝缘层覆盖第一至第四晶体管。绝缘层中的插塞连接到第一栅极结构，第二栅极结构，第一源极区域，第一漏极区域，第二源极区域或第二漏极区域。接线连接到插头。

7. 发明申请

US20060126419A1 Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block 失效
标题翻译：配置存储单元阵列块的方法，寻址方法，半导体存储器件和存储单元阵列块
公开(公告)号：US20060126419A1
公开(公告)日：2006-06-15
申请号：US11302606
申请日：2005-12-14
申请人： Sang-Pyo Hong , Du-Yeul Kim
发明人： Sang-Pyo Hong , Du-Yeul Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.
摘要翻译：配置存储单元阵列块的方法包括将第一单元逻辑块划分为子阵列块并将子阵列块的一部分分配给第二单位逻辑块，其中存储单元阵列块对应于子阵列块和第二单元逻辑块，并且子阵列块的部分和第二单元逻辑块共享外围电路。第一单元逻辑块可以基于字线的单位和/或位线的单位被划分为子阵列块。外围电路可以包括行解码器，列解码器，读出放大器和/或均衡/预充电电路。还提供了相关寻址方法，存储单元阵列块和半导体存储器件。

8. 发明申请

US20050088603A1 Seal pattern for liquid crystal display device 有权
标题翻译：液晶显示装置的密封图案
公开(公告)号：US20050088603A1
公开(公告)日：2005-04-28
申请号：US10989502
申请日：2004-11-17
申请人： Sang-Pyo Hong
发明人： Sang-Pyo Hong
IPC分类号： G02F1/1339
CPC分类号： G02F1/1339
摘要： A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternately in correspondence with the first and second openings.
摘要翻译：用于液晶显示装置的密封图案包括具有有效面积和非有效面积的基底，主密封图案，其具有布置在活性区域和非活性区域之间的边界中的注入孔，以及第一，第二和/ 非活性区域中的第三虚拟密封图案沿着与具有喷射孔的主密封图案的一部分相同的方向布置并彼此间隔开。第一和第二虚拟密封图案具有对应于注入孔的相对端的第一和第二开口。第三虚拟密封图案具有与第一和第二开口相对应地交替设置的第三，第四和第五开口。

9. 发明授权

US06919949B2 Seal pattern for liquid crystal display device including inner seal with first and second openings 有权
标题翻译：液晶显示装置的密封图案包括具有第一和第二开口的内部密封
公开(公告)号：US06919949B2
公开(公告)日：2005-07-19
申请号：US10989502
申请日：2004-11-17
申请人： Sang-Pyo Hong
发明人： Sang-Pyo Hong
IPC分类号： G02F1/1339
CPC分类号： G02F1/1339
摘要： A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternatively in correspondence with the first and second openings.
摘要翻译：用于液晶显示装置的密封图案包括具有有效面积和非有效面积的基底，主密封图案，其具有布置在活性区域和非活性区域之间的边界中的注入孔，以及第一，第二和/ 非活性区域中的第三虚拟密封图案沿着与具有喷射孔的主密封图案的一部分相同的方向布置并彼此间隔开。第一和第二虚拟密封图案具有对应于注入孔的相对端的第一和第二开口。第三虚拟密封图案具有与第一和第二开口相对应地交替布置的第三，第四和第五开口。

10. 发明申请

US20050018513A1 Temperature detection circuit and temperature detection method 有权
标题翻译：温度检测电路和温度检测方法
公开(公告)号：US20050018513A1
公开(公告)日：2005-01-27
申请号：US10875003
申请日：2004-06-22
申请人： Sang-Pyo Hong
发明人： Sang-Pyo Hong
IPC分类号： G11C7/04 , G11C11/406
CPC分类号： G11C7/04 , G11C5/143 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C29/02 , G11C29/50016 , G11C2029/5002
摘要： A temperature detection circuit and method are provided. The temperature detection circuit samples a first delay time for an input signal at a target temperature to be detected, stores a first addresses generated as the sampled result, samples a second delay time for the input address at a present operating temperature, compares a second addresses generated as the sampled result with the first addresses, and generates a detection signal if the target temperature to be detected is the same as the present operating temperature. The temperature detection method is performed by the temperature detection circuit.
摘要翻译：提供了一种温度检测电路和方法。温度检测电路对要检测的目标温度的输入信号采样第一延迟时间，存储作为采样结果产生的第一地址，对当前工作温度下的输入地址采样第二延迟时间，比较第二地址产生为具有第一地址的采样结果，并且如果要检测的目标温度与当前工作温度相同，则产生检测信号。温度检测方法由温度检测电路进行。

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