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    • 2. 发明授权
    • Method and apparatus for generating a low-density parity check code
    • 用于生成低密度奇偶校验码的方法和装置
    • US07536623B2
    • 2009-05-19
    • US11289300
    • 2005-11-30
    • Sang-Hyo KimHan-Ju KimMin-Goo KimYoung-Mo Gu
    • Sang-Hyo KimHan-Ju KimMin-Goo KimYoung-Mo Gu
    • H03M13/13
    • H03M13/6362H03M13/116H03M13/118H03M13/1185H03M13/1188
    • A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N−K) rows for check nodes and N columns for variable nodes are formed to encode an information sequence of length K to a codeword of length N. The parity check matrix is divided into an information part matrix with K columns and a parity part matrix with (N−k) columns. The parity part is divided into P×P subblocks. P is a divisor of (N−K). First and second diagonals are defined in the parity part matrix and the second diagonal is a shift of the first diagonal by f subblocks. Shifted identity matrices are placed on the first and second diagonals and zero matrices are filled elsewhere. An odd number of delta matrices each having only one element of 1 are placed in one subblock column of the parity part matrix. The parity check matrix is stored.
    • 提供了一种低密度奇偶校验(LDPC)码生成方法和装置。 形成具有用于校验节点的(NK)行和用于可变节点的N列的奇偶校验矩阵,以将长度为K的信息序列编码为长度为N的码字。奇偶校验矩阵被划分为具有K列的信息部分矩阵, 具有(Nk)列的奇偶校验部分矩阵。 奇偶校验部分分为PxP子块。 P是(N-K)的除数。 在奇偶校验部分矩阵中定义第一和第二对角线,第二对角线是第一对角线由f子块的移位。 移位的身份矩阵放置在第一和第二个对角线上,零矩阵填充到别处。 每个仅具有1个元素的奇数数量的Δ矩阵被放置在奇偶校验部分矩阵的一个子块列中。 存储奇偶校验矩阵。
    • 10. 发明授权
    • Method and apparatus for decoding low density parity check code using united node processing
    • 使用联合节点处理解码低密度奇偶校验码的方法和装置
    • US07454685B2
    • 2008-11-18
    • US11283732
    • 2005-11-22
    • Sang-Hyo KimSung-Jin ParkHan-Ju KimMin-Goo Kim
    • Sang-Hyo KimSung-Jin ParkHan-Ju KimMin-Goo Kim
    • H03M13/00
    • H03M13/1137H03M13/1114H03M13/114H03M13/116
    • A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.
    • 提供了一种解码包括多个校验节点和多个可变节点的LDPC码的方法和装置。 该装置包括校验节点选择调度器,该校验节点选择调度器选择校验节点中的至少一个,将可变节点的输入LLR值存储为初始LLR值的LLR存储器,并且存储用于连接到所选校验节点的变量节点的更新的LLR值 以及检查节点消息存储器,其将选择的校验节点上指示校验节点处理的结果值的校验节点消息存储。 该装置还包括至少一个联合节点处理器,其通过从从LLR存储器读取的相应LLR值中减去所选择的校验节点的校验节点消息来生成变量节点消息,对变量节点消息执行校验节点处理,计算LLR 通过将变量节点消息添加到校验节点处理结果值来更新值,并将计算出的LLR值传递给LLR存储器。