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1. 发明授权

US09281818B2 Interface circuit, and semiconductor device and liquid crystal display device including the same 有权
标题翻译：接口电路，半导体器件和包括其的液晶显示器件
公开(公告)号：US09281818B2
公开(公告)日：2016-03-08
申请号：US12972780
申请日：2010-12-20
申请人： Sang-Hoon Lim , Ji-Hyun Lee , Jae-youn Lee
发明人： Sang-Hoon Lim , Ji-Hyun Lee , Jae-youn Lee
IPC分类号： H03K19/094 , H03K19/0175 , H03K19/00 , H03K19/0185 , G09G3/36
CPC分类号： H03K19/0016 , G09G3/3611 , G09G2330/022 , G09G2330/027 , G09G2330/04 , H03K19/018521
摘要： A method of reducing power consumption caused by leakage current in an interface circuit between modules that are driven by different power sources is disclosed. The interface circuit includes an output driver that operates by a first power supply voltage in a first mode and does not operate in a second mode in which the first power supply voltage is prevented from being applied, an input buffer that is operated by a second power supply voltage in the first and second modes, and a transmission line that connects an output terminal of the output driver to an input terminal of the input buffer. The interface circuit further includes a current leakage prevention circuit that prevents, in the second mode, a current leakage in the input buffer between a second power supply voltage source that supplies the second power supply voltage and a ground voltage source.
摘要翻译：公开了一种降低由不同电源驱动的模块之间的接口电路中的漏电流引起的功耗的方法。接口电路包括：输出驱动器，其以第一模式的第一电源电压工作，并且不工作在第二模式，其中防止第一电源电压被施加;输入缓冲器，由第二电源第一模式和第二模式中的电源电压，以及将输出驱动器的输出端子连接到输入缓冲器的输入端子的传输线。接口电路还包括漏电流电路，其防止在第二模式中在提供第二电源电压的第二电源电压源和地电压源之间的输入缓冲器中的电流泄漏。

2. 发明申请

US20110157251A1 INTERFACE CIRCUIT, AND SEMICONDUCTOR DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THE SAME 有权
标题翻译：接口电路和半导体器件以及包括其的液晶显示器件
公开(公告)号：US20110157251A1
公开(公告)日：2011-06-30
申请号：US12972780
申请日：2010-12-20
申请人： Sang-Hoon Lim , Ji-Hyun Lee , Jae-youn Lee
发明人： Sang-Hoon Lim , Ji-Hyun Lee , Jae-youn Lee
IPC分类号： G09G5/10 , H03K19/0175 , G09G3/36
CPC分类号： H03K19/0016 , G09G3/3611 , G09G2330/022 , G09G2330/027 , G09G2330/04 , H03K19/018521
摘要： A method of reducing power consumption caused by leakage current in an interface circuit between modules that are driven by different power sources is disclosed. The interface circuit includes an output driver that operates by a first power supply voltage in a first mode and does not operate in a second mode in which the first power supply voltage is prevented from being applied, an input buffer that is operated by a second power supply voltage in the first and second modes, and a transmission line that connects an output terminal of the output driver to an input terminal of the input buffer. The interface circuit further includes a current leakage prevention circuit that prevents, in the second mode, a current leakage in the input buffer between a second power supply voltage source that supplies the second power supply voltage and a ground voltage source.
摘要翻译：公开了一种降低由不同电源驱动的模块之间的接口电路中的漏电流引起的功耗的方法。接口电路包括：输出驱动器，其以第一模式的第一电源电压工作，并且不工作在第二模式，其中防止第一电源电压被施加;输入缓冲器，由第二电源第一模式和第二模式中的电源电压，以及将输出驱动器的输出端子连接到输入缓冲器的输入端子的传输线。接口电路还包括漏电流电路，其防止在第二模式中在提供第二电源电压的第二电源电压源和地电压源之间的输入缓冲器中的电流泄漏。

3. 发明申请

US20090315528A1 INTERNAL SUPPLY VOLTAGE GENERATOR CAPABLE OF REDUCING LATCH-UP AND SEMICONDUCTOR DEVICE HAVING THE SAME 失效
标题翻译：具有减少具有相同功能的锁存器和半导体器件的内部电源电压发生器
公开(公告)号：US20090315528A1
公开(公告)日：2009-12-24
申请号：US12488117
申请日：2009-06-19
申请人： Byung-ho Choi , Jae-youn Lee
发明人： Byung-ho Choi , Jae-youn Lee
IPC分类号： G05F1/10
CPC分类号： H01L27/0921
摘要： Provided are an internal supply voltage generator capable of reducing latch-up and a semiconductor device having the same. The internal supply voltage generator generates at least one internal supply voltage, and includes a first booster circuit that generates a first voltage from a first reference voltage and an input voltage and outputs the first voltage via a first output terminal, a second booster circuit that generates a third voltage from a second voltage and the first voltage and outputs the third voltage via a second output terminal, and at least one switch that is disposed to correspond to at least one of the first output terminal and the second output terminal and adjusts at least one of the first voltage and the third voltage.
摘要翻译：提供能够减少闩锁的内部电源电压发生器和具有该闩锁的半导体器件。内部电源电压发生器产生至少一个内部电源电压，并且包括第一升压电路，其从第一参考电压和输入电压产生第一电压，并经由第一输出端输出第一电压;第二升压电路，其产生来自第二电压的第三电压和第一电压，并且经由第二输出端输出第三电压，以及至少一个开关，其设置为对应于第一输出端子和第二输出端子中的至少一个，并且至少调节第一电压和第三电压之一。

4. 发明授权

US07737939B2 Display driver IC and display driving method for supporting various driving modes 失效
标题翻译：显示驱动IC和显示驱动方式，支持各种驾驶模式
公开(公告)号：US07737939B2
公开(公告)日：2010-06-15
申请号：US11564884
申请日：2006-11-30
申请人： Dong-hyuk Shin , Jae-youn Lee , Jee-hwal Kim
发明人： Dong-hyuk Shin , Jae-youn Lee , Jee-hwal Kim
IPC分类号： G09G3/36
CPC分类号： G09G3/3622 , G09G3/2092 , G09G3/3681 , G09G2300/0426 , G09G2310/021 , G09G2310/0218
摘要： A display driving integrated circuit (IC) and a display driving method for supporting various driving mode include an input unit, a digital-analog converter and a row data output unit. The row data output unit outputs at least one of the row data to a row line corresponding thereto for each row scan clock pulse. The row data output unit activates output paths for outputting the row data to the row lines in an activation order of a driving mode selected from a plurality of driving modes having different orders of activating the output paths in response to a mode select signal.
摘要翻译：用于支持各种驱动模式的显示驱动集成电路（IC）和显示驱动方法包括输入单元，数模转换器和行数据输出单元。行数据输出单元将行数据中的至少一个输出到与每行行扫描时钟脉冲对应的行线。行数据输出单元激活输出路径，用于以从响应于模式选择信号激活输出路径的不同顺序的多个驱动模式中选择的驱动模式的激活顺序，将行数据输出到行线。

5. 发明申请

US20070165014A1 Display Driver IC and Display Driving Method for Supporting Various Driving Modes 失效
标题翻译：显示驱动IC和显示驱动方式支持各种驱动模式
公开(公告)号：US20070165014A1
公开(公告)日：2007-07-19
申请号：US11564884
申请日：2006-11-30
申请人： Dong-hyuk Shin , Jae-youn Lee , Jee-hwal Kim
发明人： Dong-hyuk Shin , Jae-youn Lee , Jee-hwal Kim
IPC分类号： G09G5/00
CPC分类号： G09G3/3622 , G09G3/2092 , G09G3/3681 , G09G2300/0426 , G09G2310/021 , G09G2310/0218
摘要： A display driving integrated circuit (IC) and a display driving method for supporting various driving mode include an input unit, a digital-analog converter and a row data output unit. The row data output unit outputs at least one of the row data to a row line corresponding thereto for each row scan clock pulse. The row data output unit activates output paths for outputting the row data to the row lines in an activation order of a driving mode selected from a plurality of driving modes having different orders of activating the output paths in response to a mode select signal.
摘要翻译：用于支持各种驱动模式的显示驱动集成电路（IC）和显示驱动方法包括输入单元，数模转换器和行数据输出单元。行数据输出单元将行数据中的至少一个输出到与每行行扫描时钟脉冲对应的行线。行数据输出单元激活输出路径，用于以从响应于模式选择信号激活输出路径的不同顺序的多个驱动模式中选择的驱动模式的激活顺序，将行数据输出到行线。

6. 发明授权

US06836186B2 AB class amplifier for controlling quiescent current 有权
标题翻译：用于控制静态电流的AB级放大器
公开(公告)号：US06836186B2
公开(公告)日：2004-12-28
申请号：US10417680
申请日：2003-04-17
申请人： Jae-youn Lee , Jun-seok Han
发明人： Jae-youn Lee , Jun-seok Han
IPC分类号： H03F310
CPC分类号： H03F1/0261 , H03F1/307 , H03F3/3022
摘要： An AB class buffer amplifier controls quiescent current. The AB class buffer amplifier includes a first current controller and a second current controller. The first current controller sources current to an output node in response to a first logic level of a first signal, and buffers and outputs an input voltage to the output node in response to a second logic level of the first signal. The second current controller sinks the current from the output node in response to a second logic level of a second signal, and buffers and outputs the input voltage to the output node in response to a first logic level of the second signal. The first and second signals are generated at the first logic levels if the input voltage is higher than the output voltage and at the second logic level if the input voltage is lower than the output voltage. The AB class buffer amplifier may further include comparing unit which compares the input voltage with an output voltage from the output node and generates the first and second signals in response to the compared results. The comparing unit includes first and second comparators. Accordingly, the AB class buffer amplifier can drive an external circuit using high currents by freely controlling the amount of quiescent current, and easily sourcing and sinking quiescent current flowing to an output node of the amplifier.
摘要翻译： AB级缓冲放大器控制静态电流。 AB级缓冲放大器包括第一电流控制器和第二电流控制器。第一电流控制器响应于第一信号的第一逻辑电平将电流馈送到输出节点，并且响应于第一信号的第二逻辑电平缓冲并输出输入电压到输出节点。第二电流控制器响应于第二信号的第二逻辑电平而从输出节点吸收电流，并且响应于第二信号的第一逻辑电平缓冲并输出输入电压到输出节点。如果输入电压高于输出电压，则在第一逻辑电平处产生第一和第二信号，如果输入电压低于输出电压，则产生第二逻辑电平。 AB类缓冲放大器还可以包括比较单元，其将输入电压与来自输出节点的输出电压进行比较，并响应于比较结果产生第一和第二信号。比较单元包括第一和第二比较器。因此，AB级缓冲放大器可以通过自由地控制静态电流的量来驱动外部电路，并且容易地产生和吸收流向放大器的输出节点的静态电流。

7. 发明授权

US08674750B2 Charge pump, a method for controlling the same, and a display driving system comprising the charge pump 有权
标题翻译：电荷泵，其控制方法以及包括电荷泵的显示驱动系统
公开(公告)号：US08674750B2
公开(公告)日：2014-03-18
申请号：US13053750
申请日：2011-03-22
申请人： Jae-youn Lee
发明人： Jae-youn Lee
IPC分类号： G05F1/10
CPC分类号： G09G3/3696 , H02M3/073
摘要： Disclosed is a charge pump and a method of controlling the charge pump. The charge pump including a charge pumping unit to boost a first voltage in response to a clock signal, the first voltage being boosted to a second voltage having a voltage level higher than the first voltage by a middle voltage, the middle voltage being generated in response to a first control signal, the first control signal being enabled during a time period in which the clock signal and a second control signal are disabled. The charge pumping unit boosts the second voltage to a third voltage, the third voltage being a voltage level higher than an input voltage by the first voltage, the input voltage being generated in response to the second control signal. The charge pump includes a first transfer unit to output the third voltage in response to the second control signal.
摘要翻译：公开了电荷泵和控制电荷泵的方法。所述电荷泵包括电荷泵送单元，用于响应于时钟信号升高第一电压，所述第一电压被升压到具有高于所述第一电压的电压电平的中间电压的第二电压，所述中间电压作为响应产生对于第一控制信号，在禁止时钟信号和第二控制信号的时间段期间，第一控制信号被使能。电荷泵送单元将第二电压升高到第三电压，第三电压是比第一电压高于输入电压的电压电平，输入电压是响应于第二控制信号产生的。电荷泵包括响应于第二控制信号输出第三电压的第一传送单元。

8. 发明授权

US08004347B2 Internal supply voltage generator capable of reducing latch-up and semiconductor device having the same 失效
标题翻译：能够减少闩锁的内部电源电压发生器和具有该闩锁的半导体器件
公开(公告)号：US08004347B2
公开(公告)日：2011-08-23
申请号：US12488117
申请日：2009-06-19
申请人： Byung-ho Choi , Jae-youn Lee
发明人： Byung-ho Choi , Jae-youn Lee
IPC分类号： G05F3/08 , H02M3/00
CPC分类号： H01L27/0921
摘要： Provided are an internal supply voltage generator capable of reducing latch-up and a semiconductor device having the same. The internal supply voltage generator generates at least one internal supply voltage, and includes a first booster circuit that generates a first voltage from a first reference voltage and an input voltage and outputs the first voltage via a first output terminal, a second booster circuit that generates a third voltage from a second voltage and the first voltage and outputs the third voltage via a second output terminal, and at least one switch that is disposed to correspond to at least one of the first output terminal and the second output terminal and adjusts at least one of the first voltage and the third voltage.
摘要翻译：提供能够减少闩锁的内部电源电压发生器和具有该闩锁的半导体器件。内部电源电压发生器产生至少一个内部电源电压，并且包括第一升压电路，其从第一参考电压和输入电压产生第一电压，并经由第一输出端输出第一电压;第二升压电路，其产生来自第二电压的第三电压和第一电压，并且经由第二输出端输出第三电压，以及至少一个开关，其设置为对应于第一输出端子和第二输出端子中的至少一个，并且至少调节第一电压和第三电压之一。

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