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1. 发明授权

US07453713B2 Dual chip package 有权
标题翻译：双芯片封装
公开(公告)号：US07453713B2
公开(公告)日：2008-11-18
申请号：US11700839
申请日：2007-02-01
申请人： Hyung-Min Kim , Sang-Chul Kang , Jin-Yub Lee
发明人： Hyung-Min Kim , Sang-Chul Kang , Jin-Yub Lee
IPC分类号： G11C5/06
CPC分类号： G11C8/12 , G11C16/10 , H01L25/065 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.
摘要翻译：本发明涉及连接到主机并且包括第一存储器芯片和第二存储器芯片的双芯片封装。第一和第二存储器芯片中的每一个包括闪速存储器; 连接到第一或第二电压的选项焊盘; 寄存器，被配置为存储指示是否选择存储器芯片的标志信号; 比较器电路，被配置为将存储在所述寄存器中的标志信号与在所述选项焊盘处显现的逻辑值进行比较以产生闪存存取信号。第一和第二存储器芯片中的每一个还包括被配置为响应于闪存访问信号访问闪速存储器的存储器控制器单元和被配置为响应于闪存访问信号向主机提供中断信号的中断控制器单元，以及从主机提供的控制信号。

2. 发明授权

US07218558B2 Semiconductor memory devices having column redundancy circuits therein that support multiple memory blocks 有权
标题翻译：其中具有支持多个存储块的列冗余电路的半导体存储器件
公开(公告)号：US07218558B2
公开(公告)日：2007-05-15
申请号：US10999182
申请日：2004-11-29
申请人： Sang-Chul Kang , Hyung-Min Kim
发明人： Sang-Chul Kang , Hyung-Min Kim
IPC分类号： G11C7/00 , G11C7/10 , G11C17/18 , G11C8/00
CPC分类号： G11C29/808 , G11C29/806
摘要： Semiconductor memory devices include a memory array having a plurality of multi-column memory blocks therein and a multi-column redundant memory block. A redundancy column selecting unit is provided, which is configured to route data read from the multi-column redundant memory block to a redundant data line, in response to a column address. A data input/output unit is also provided. This data input/output unit is connected to the redundant data line and a data line associated with a defective column in the memory array. The data input/output unit is configured to respond to an instruction to read first data from a defective column in the memory array by routing first data read from a selected redundant column in the multi-column redundant memory block to an input/output bus while concurrently blocking data read from the defective column from being transferred to the input/output bus.
摘要翻译：半导体存储器件包括其中具有多个多列存储器块的存储器阵列和多列冗余存储器块。提供冗余列选择单元，其被配置为响应于列地址将从多列冗余存储器块读取的数据路由到冗余数据线。还提供了数据输入/输出单元。该数据输入/输出单元连接到冗余数据线和与存储器阵列中的有缺陷列相关联的数据线。数据输入/输出单元被配置为通过将从多列冗余存储器块中的所选冗余列读取的第一数据路由到输入/输出总线来响应从存储器阵列中的有缺陷列读取第一数据的指令，同时同时阻止从故障列读取的数据被传送到输入/输出总线。

3. 发明申请

US20060044918A1 Semiconductor memory devices having column redundancy circuits therein that support multiple memory blocks 有权
标题翻译：其中具有支持多个存储块的列冗余电路的半导体存储器件
公开(公告)号：US20060044918A1
公开(公告)日：2006-03-02
申请号：US10999182
申请日：2004-11-29
申请人： Sang-Chul Kang , Hyung-Min Kim
发明人： Sang-Chul Kang , Hyung-Min Kim
IPC分类号： G11C8/00
CPC分类号： G11C29/808 , G11C29/806
摘要： Semiconductor memory devices include a memory array having a plurality of multi-column memory blocks therein and a multi-column redundant memory block. A redundancy column selecting unit is provided, which is configured to route data read from the multi-column redundant memory block to a redundant data line, in response to a column address. A data input/output unit is also provided. This data input/output unit is connected to the redundant data line and a data line associated with a defective column in the memory array. The data input/output unit is configured to respond to an instruction to read first data from a defective column in the memory array by routing first data read from a selected redundant column in the multi-column redundant memory block to an input/output bus while concurrently blocking data read from the defective column from being transferred to the input/output bus.
摘要翻译：半导体存储器件包括其中具有多个多列存储器块的存储器阵列和多列冗余存储器块。提供冗余列选择单元，其被配置为响应于列地址将从多列冗余存储器块读取的数据路由到冗余数据线。还提供了数据输入/输出单元。该数据输入/输出单元连接到冗余数据线和与存储器阵列中的有缺陷列相关联的数据线。数据输入/输出单元被配置为通过将从多列冗余存储器块中的所选冗余列读取的第一数据路由到输入/输出总线来响应从存储器阵列中的有缺陷列读取第一数据的指令，同时同时阻止从故障列读取的数据被传送到输入/输出总线。

4. 发明申请

US20070247930A1 Dual chip package 有权
标题翻译：双芯片封装
公开(公告)号：US20070247930A1
公开(公告)日：2007-10-25
申请号：US11700839
申请日：2007-02-01
申请人： Hyung-Min Kim , Sang-Chul Kang , Jin-Yub Lee
发明人： Hyung-Min Kim , Sang-Chul Kang , Jin-Yub Lee
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C16/10 , H01L25/065 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.
摘要翻译：本发明涉及连接到主机并且包括第一存储器芯片和第二存储器芯片的双芯片封装。第一和第二存储器芯片中的每一个包括闪速存储器; 连接到第一或第二电压的选项焊盘; 寄存器，被配置为存储指示是否选择存储器芯片的标志信号; 比较器电路，被配置为将存储在所述寄存器中的标志信号与在所述选项焊盘处显现的逻辑值进行比较以产生闪存存取信号。第一和第二存储器芯片中的每一个还包括被配置为响应于闪存访问信号访问闪速存储器的存储器控制器单元和被配置为响应于闪存访问信号向主机提供中断信号的中断控制器单元，以及从主机提供的控制信号。

5. 发明申请

US20080310226A1 Multi-Bit Flash Memory Devices Having a Single Latch Structure and Related Programming Methods, Systems and Memory Cards 有权
标题翻译：具有单个锁存结构的多位闪存器件和相关编程方法，系统和存储卡
公开(公告)号：US20080310226A1
公开(公告)日：2008-12-18
申请号：US12182274
申请日：2008-07-30
申请人： Sang-Chul Kang , Ho-Kil Lee , Jin-Yub Lee
发明人： Sang-Chul Kang , Ho-Kil Lee , Jin-Yub Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.
摘要翻译：提供多位闪存设备。该多位闪存器件包括存储单元阵列和包括页缓冲器的页缓冲块。每个页面缓冲器具有单个锁存结构，并且根据加载的数据对存储器单元执行写入操作。缓冲随机存取存储器（RAM）被配置为在多位程序操作期间存储从外部主机设备提供的程序数据。提供了控制逻辑，其被配置为控制页面缓冲区块和缓冲器RAM，使得存储在缓冲器RAM中的程序数据被重新加载到页面缓冲器块中，每当在多位程序操作之前编程的数据与当前的数据进行比较程序。控制逻辑被配置为在多位程序操作完成之前存储要在缓冲RAM中接下来被编程的数据。

6. 发明授权

US07684241B2 Flash memory devices having multi-page copyback functionality and related block replacement methods 有权
标题翻译：具有多页复印功能和相关的块替换方法的闪存设备
公开(公告)号：US07684241B2
公开(公告)日：2010-03-23
申请号：US11843902
申请日：2007-08-23
申请人： Sang-Chul Kang , Yong-Taek Jeong
发明人： Sang-Chul Kang , Yong-Taek Jeong
IPC分类号： G11C16/06
CPC分类号： G11C16/102 , G11C11/5628 , G11C16/3418
摘要： Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.
摘要翻译：提供了在非易失性存储器件中执行多页复印程序的方法，其中非易失性存储器件包括具有多个存储器块的存储器。具有第一地址的存储块的数据页被响应于所生成的多页复印程序命令而被替换。确定数据页面的第一个地址是否与检测到故障的页面的存储地址相同。如果确定第一个地址和存储的地址不相同，则第一个地址递增。替换数据页面，比较寻址的地址，并增加地址，直到确定增加的地址和存储的地址相同。本文还提供了相关设备和系统。

7. 发明授权

US07508730B2 Semiconductor memory devices having control circuitry to avoid recovering a charge pump when executing consecutive sections of a continuous operation command and methods of operating the same 有权
标题翻译：具有控制电路的半导体存储器件，用于在执行连续操作命令的连续部分时避免电荷泵的恢复及其操作方法
公开(公告)号：US07508730B2
公开(公告)日：2009-03-24
申请号：US11565016
申请日：2006-11-30
申请人： Yong-Taek Jeong , Sang-Chul Kang
发明人： Yong-Taek Jeong , Sang-Chul Kang
IPC分类号： G11C8/00
CPC分类号： G11C16/12 , G11C5/145
摘要： A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read write and/or erase data.
摘要翻译：半导体器件包括存储单元阵列和配置为从半导体存储器件的外部接收命令的命令接口。命令接口还被配置为解释所接收的命令并且确定所接收的命令是否是连续的操作命令。如果命令是连续操作命令，则命令接口输出对应于命令的命令信号和至少一个指示连续操作部分的标志信号。控制单元被配置为接收从命令接口输出的命令信号和至少一个标志信号，并且基于接收的命令信号和至少一个标志信号产生泵控制信号。电荷泵被配置为响应于泵控制信号产生电压，以用于访问存储器单元阵列以读取写入和/或擦除数据。

8. 发明申请

US20080084779A1 SEMICONDUCTOR MEMORY DEVICES HAVING CONTROL CIRCUITRY TO AVOID RECOVERING A CHARGE PUMP WHEN EXECUTING CONSECUTIVE SECTIONS OF A CONTINUOUS OPERATION COMMAND AND METHODS OF OPERATING THE SAME 有权
标题翻译：具有控制电路的半导体存储器件，当执行连续操作命令的连续部分时，避免恢复充电泵及其操作方法
公开(公告)号：US20080084779A1
公开(公告)日：2008-04-10
申请号：US11565016
申请日：2006-11-30
申请人： Yong-Taek Jeong , Sang-Chul Kang
发明人： Yong-Taek Jeong , Sang-Chul Kang
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C16/12 , G11C5/145
摘要： A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read right and/or erase data.
摘要翻译：半导体器件包括存储单元阵列和配置为从半导体存储器件的外部接收命令的命令接口。命令接口还被配置为解释所接收的命令并且确定所接收的命令是否是连续的操作命令。如果命令是连续操作命令，则命令接口输出对应于命令的命令信号和至少一个指示连续操作部分的标志信号。控制单元被配置为接收从命令接口输出的命令信号和至少一个标志信号，并且基于接收的命令信号和至少一个标志信号产生泵控制信号。电荷泵被配置为响应于泵控制信号产生电压，以用于访问存储单元阵列以读取和/或擦除数据。

9. 发明申请

US20080052445A1 FLASH MEMORY DEVICES INCLUDING BLOCK INFORMATION BLOCKS AND METHODS OF OPERATING SAME 审中-公开
标题翻译：包括块信息块的闪存存储器件及其操作方法
公开(公告)号：US20080052445A1
公开(公告)日：2008-02-28
申请号：US11669553
申请日：2007-01-31
申请人： Eun-Kyoung Kim , Hyun-Sun Mo , Sang-Chul Kang
发明人： Eun-Kyoung Kim , Hyun-Sun Mo , Sang-Chul Kang
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C16/04 , G11C29/76 , G11C2229/723
摘要： Disclosed is a semiconductor memory device including pluralities of memory blocks each of which is segmented into main and spare regions, and a block information storing region storing block information of the memory blocks.
摘要翻译：公开了一种半导体存储器件，其包括多个存储块，每个存储块被分割成主区域和备用区域，以及块信息存储区域，存储存储块的块信息。

10. 发明授权

US07272048B2 Nonvolatile memory device controlling common source line for improving read characteristic 失效
标题翻译：非易失性存储器件控制公共源极线，以提高读取特性
公开(公告)号：US07272048B2
公开(公告)日：2007-09-18
申请号：US11194945
申请日：2005-08-01
申请人： Sang-Chul Kang , Jin-Yub Lee
发明人： Sang-Chul Kang , Jin-Yub Lee
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/24 , G11C16/0483
摘要： A non-volatile memory device capable of improving a read characteristic includes memory blocks, each memory block having a plurality of word lines. A common source line is arranged to be shared by the memory blocks. A first transistor is connected to the common source line, and a voltage higher than a power supply voltage is applied to a gate of the first transistor during a read operation. A second transistor connects the first transistor to a reference voltage during the read operation.
摘要翻译：能够改善读取特性的非易失性存储器件包括存储块，每个存储块具有多个字线。公共源线被布置成由存储器块共享。第一晶体管连接到公共源极线，并且在读取操作期间，将高于电源电压的电压施加到第一晶体管的栅极。在读取操作期间，第二晶体管将第一晶体管连接到参考电压。

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