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1. 发明授权

US6060759A Method and apparatus for creating improved inductors for use with electronic oscillators 失效
标题翻译：用于产生用于电子振荡器的改进的电感器的方法和装置
公开(公告)号：US6060759A
公开(公告)日：2000-05-09
申请号：US36187
申请日：1998-03-06
申请人： Sang Hoo Dhong , Uttam Shymalindu Ghoshal , Kyung Tek Lee
发明人： Sang Hoo Dhong , Uttam Shymalindu Ghoshal , Kyung Tek Lee
IPC分类号： H01F17/00 , H01L21/02 , H01L27/08 , H01L29/00
CPC分类号： H01F17/0033 , H01L27/08 , H01L28/10
摘要： The present invention relates, in general, to a method and apparatus for creating improved inductors which can be adapted for use with electronic oscillators. The method includes at least the following: forming a first coil; forming a second coil, such that the second coil is proximate to the first coil and such that a magnetic flux from the formed outer coil will link with a magnetic flux of the formed second coil; and connecting the first coil to the second coil in electrical parallel. The apparatus includes at least the following: a substrate; and a composite inductor having at least a first coil with an associated inductance and resistance and a second coil with an associated inductance and resistance, with the first coil and the second coil connected in electrical parallel but formed in the substrate such that said composite inductor has resistance substantially less than the combined resistances associated with the first coil and the second coil. The composite inductor further includes the first coil and second coil connected in electrical parallel but formed in the substrate such that the composite inductor has inductances substantially equivalent to the combined inductances associated with the first coil and the second coil. The apparatus can be utilized to form an oscillator implemented in an integrated circuit.
摘要翻译：本发明一般涉及一种用于产生可适用于电子振荡器的改进电感器的方法和装置。该方法至少包括以下：形成第一线圈; 形成第二线圈，使得所述第二线圈靠近所述第一线圈，并且使得来自所形成的外部线圈的磁通将与所形成的第二线圈的磁通量相连; 并且将第一线圈电连接到第二线圈。该装置至少包括以下：基板; 以及复合电感器，其具有至少具有相关联的电感和电阻的第一线圈和具有相关联的电感和电阻的第二线圈，其中所述第一线圈和所述第二线圈电平行连接但形成在所述基板中，使得所述复合电感器具有电阻基本上小于与第一线圈和第二线圈相关联的组合电阻。复合电感器还包括第一线圈和第二线圈，该第一线圈和第二线圈并联连接而形成在衬底中，使得复合电感器具有与第一线圈和第二线圈相关联的组合电感基本相等的电感。该装置可以用于形成在集成电路中实现的振荡器。

2. 发明授权

US06594679B1 Leading-zero anticipator having an independent sign bit determination module 有权
标题翻译：具有独立符号位确定模块的前零预测器
公开(公告)号：US06594679B1
公开(公告)日：2003-07-15
申请号：US09531850
申请日：2000-03-20
申请人： Kyung Tek Lee , Kevin John Nowka , Sang Hoo Dhong
发明人： Kyung Tek Lee , Kevin John Nowka , Sang Hoo Dhong
IPC分类号： G06F1500
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936 , G06F7/5443
摘要： A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.
摘要翻译：公开了一种具有独立符号位确定模块的前置零预测器。用于预测浮点处理器内的加法器的前导零的装置包括前置零预测器和符号确定模块。前导零预测器通过检查进位传播，产生和杀死加法器的两个输入操作数的两个相邻位来产生前导零字符串和前导字符串。前导零字符串用于正和，并且前导字符串用于负和。独立于前置零预测器，符号确定模块根据前置零预测器中的操作来确定加法器的输出的符号。

3. 发明授权

US06360238B1 Leading zero/one anticipator having an integrated sign selector 失效
标题翻译：领先的零/一个预测器具有集成的符号选择器
公开(公告)号：US06360238B1
公开(公告)日：2002-03-19
申请号：US09270469
申请日：1999-03-15
申请人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F501
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.
摘要翻译：公开了具有集成符号选择器的零/一预测器。通过检查对浮点处理器内的加法器的两个输入操作数的两个相邻位进行传播，产生和杀死，产生前导零字符串和前导字符串。前导零字符串为正和，前导字符串为负数。然后从前导零字符串和前导字符串确定归一化偏移量。然后分别确定两个输入操作数的和的符号，但与归一化偏移量确定处理同时确定。然后，利用该符号来选择正和或负的正和归一化移位量。

4. 发明授权

US07746140B2 Scannable latch 有权
标题翻译：可扫描闩锁
公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

5. 发明授权

US07716516B2 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

6. 发明授权

US07710796B2 Level shifter for boosting wordline voltage and memory cell performance 有权
标题翻译：电平移位器用于提高字线电压和存储单元性能
公开(公告)号：US07710796B2
公开(公告)日：2010-05-04
申请号：US11935741
申请日：2007-11-06
申请人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
发明人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译：电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。电平移位器耦合在第一电路和第二电路之间。电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个的操作。

7. 发明授权

US07447725B2 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US07447725B2
公开(公告)日：2008-11-04
申请号：US10982110
申请日：2004-11-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

8. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

9. 发明授权

US07406589B2 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US07406589B2
公开(公告)日：2008-07-29
申请号：US11127848
申请日：2005-05-12
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/552 , G06F7/544 , G06F7/38
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

10. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

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