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1. 发明授权

US07157977B2 Automatic gain control feedback amplifier 有权
标题翻译：自动增益控制反馈放大器
公开(公告)号：US07157977B2
公开(公告)日：2007-01-02
申请号：US10995033
申请日：2004-11-23
申请人： Sang Heung Lee , Hyeon Cheol Ki , Jin Yeong Kang , Kyu Hwan Shim , Kyong Ik Cho
发明人： Sang Heung Lee , Hyeon Cheol Ki , Jin Yeong Kang , Kyu Hwan Shim , Kyong Ik Cho
IPC分类号： H03F3/08
CPC分类号： H03F3/08 , H03F1/34 , H03F3/3432 , H03F3/50 , H03G3/3084
摘要： There is provided a feedback amplifier capable of easily controlling its dynamic range without a separate gain control signal generation circuit. The feedback amplifier includes an input terminal detecting an input voltage from input current, a feedback amplification unit amplifying the input voltage to generate an output signal, and an output terminal outputting a signal amplified by the feedback amplification unit. The feedback amplification unit includes a feedback circuit unit including a feedback resistor located between the input terminal and the output terminal, and a feedback transistor connected in parallel to the feedback resistor; and a bias circuit unit supplying a predetermined bias voltage to the feedback transistor of the feedback circuit unit and merged in the feedback amplification unit.
摘要翻译：提供了一种反馈放大器，其能够在没有单独的增益控制信号产生电路的情况下容易地控制其动态范围。反馈放大器包括检测来自输入电流的输入电压的输入端子，放大输入电压以产生输出信号的反馈放大单元，以及输出由反馈放大单元放大的信号的输出端子。反馈放大单元包括反馈电路单元，该反馈电路单元包括位于输入端子和输出端子之间的反馈电阻器和与反馈电阻器并联连接的反馈晶体管; 以及偏置电路单元，向反馈电路单元的反馈晶体管提供预定的偏置电压并且合并在反馈放大单元中。

2. 发明授权

US07741665B2 High-quality CMOS image sensor and photo diode 有权
标题翻译：高质量CMOS图像传感器和光电二极管
公开(公告)号：US07741665B2
公开(公告)日：2010-06-22
申请号：US11872922
申请日：2007-10-16
申请人： Jin Yeong Kang , Jin Gun Koo , Sang Heung Lee
发明人： Jin Yeong Kang , Jin Gun Koo , Sang Heung Lee
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14689 , H01L27/14609
摘要： Provided are a high-quality CMOS image sensor and a photo diode, which can be fabricated in sub-90 nm regime using nanoscale CMOS technology. The photo diode includes: a p-type well; an internal n-type region formed under a surface of the p-type well; and a surface p-type region including a highly doped p-type SiGeC epitaxial layer or a polysilicon layer deposited on a top surface of the p-type well over the internal n-type region. The image sensor includes: a photo diode including an internal n-type region and a surface p-type region; a transfer transistor for transmitting photo-charges generated in the photo diode to a floating diffusion node; and a driving transistor for amplifying a variation in an electric potential of the floating diffusion node due to the photo-charges. The image sensor further includes a floating metal layer for functioning as the floating diffusion node and applying an electric potential from a drain of the transfer transistor to a gate of the driving transistor.
摘要翻译：提供了一种高质量CMOS图像传感器和光电二极管，其可以使用纳米级CMOS技术在亚90nm范围内制造。光电二极管包括：p型阱; 形成在p型阱的表面下的内部n型区域; 以及表面p型区域，其包括在内部n型区域上沉积在p型阱的顶表面上的高掺杂p型SiGeC外延层或多晶硅层。图像传感器包括：包含内部n型区域和表面p型区域的光电二极管; 用于将在光电二极管中产生的光电荷传输到浮动扩散节点的传输晶体管; 以及用于放大由于光电荷引起的浮动扩散节点的电位变化的驱动晶体管。图像传感器还包括浮动金属层，用作浮动扩散节点并将电势从传输晶体管的漏极施加到驱动晶体管的栅极。

3. 发明授权

US07902577B2 Image sensor having heterojunction bipolar transistor and method of fabricating the same 有权
标题翻译：具有异质结双极晶体管的图像传感器及其制造方法
公开(公告)号：US07902577B2
公开(公告)日：2011-03-08
申请号：US11872308
申请日：2007-10-15
申请人： Jin Yeong Kang , Sang Heung Lee , Jin Gun Koo
发明人： Jin Yeong Kang , Sang Heung Lee , Jin Gun Koo
IPC分类号： H01L31/11
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14681
摘要： Provided is an image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by SiGe BiCMOS technology. In the image sensor, a PD employs a floating-base-type SiGe HBT. A floating base of the SiGe HBT produces a positive voltage with respect to a collector during an exposure process, and the HBT performs a reverse bipolar operation due to the positive voltage so that the collector and an emitter exchange functions. The SiGe HBT can sense an optical current signal and also amplify the optical current signal. The image sensor requires only three transistors in a pixel so that the degree of integration can increase. The image sensor has an improved sensitivity of signals in the short wavelength region and a sensing signal has excellent linearity such that both a sensing mechanism and control circuit are very simple.
摘要翻译：提供了具有异质结双极晶体管（HBT）的图像传感器及其制造方法。图像传感器由SiGe BiCMOS技术制造。在图像传感器中，PD采用浮动型SiGe HBT。 SiGe HBT的浮动基极在曝光过程中产生相对于集电极的正电压，HBT由于正电压而执行反向双极性操作，从而集电极和发射极交换功能起作用。 SiGe HBT可以感测光电流信号，并且还可以放大光电流信号。图像传感器在像素中仅需要三个晶体管，使得集成度可以增加。图像传感器在短波长区域具有改善的信号灵敏度，并且感测信号具有优异的线性度，使得感测机构和控制电路都非常简单。

4. 发明授权

US07170355B2 Voltage-controlled oscillator using current feedback network 有权
标题翻译：使用电流反馈网络的压控振荡器
公开(公告)号：US07170355B2
公开(公告)日：2007-01-30
申请号：US10957749
申请日：2004-10-05
申请人： Ja Yol Lee , Sang Heung Lee , Jin Yeong Kang , Seung Hyeub Oh
发明人： Ja Yol Lee , Sang Heung Lee , Jin Yeong Kang , Seung Hyeub Oh
IPC分类号： H03B1/00
CPC分类号： H03B5/1231 , H03B5/1215 , H03B5/1221 , H03B5/1243
摘要： Provided is a voltage-controlled oscillator (VCO) using a current feedback network for use in a wireless communication terminal. The voltage-controlled oscillator has high input impedance and low output impedance, so that a degree of isolation from the external load is excellent, thereby preventing degradation of the Q-factor by the load in overall oscillation circuit. In the voltage-controlled oscillator of the present invention, an LC resonator is provided to generate positive feedback, and negative resistance may be obtained at a wider frequency range by tuning a varactor of the LC resonator. And a boosting inductor is inserted into the positive feedback loop to have a greater negative resistance, therefore it is possible to prevent a problem in which the oscillation does not occur due to the parasitic resistance components generated during circuit fabrication.
摘要翻译：提供了一种使用电流反馈网络在无线通信终端中使用的压控振荡器（VCO）。压控振荡器具有高输入阻抗和低输出阻抗，使得与外部负载的隔离度优异，从而防止整个振荡电路中的负载对Q因子的劣化。在本发明的压控振荡器中，设置LC谐振器以产生正反馈，并且通过调谐LC谐振器的变容二极管可以在更宽的频率范围内获得负电阻。并且将增压电感器插入到正反馈回路中以具有更大的负电阻，因此可以防止由于在电路制造期间产生的寄生电阻分量而不发生振荡的问题。

5. 发明授权

US07550796B2 Germanium semiconductor device and method of manufacturing the same 有权
标题翻译：锗半导体器件及其制造方法
公开(公告)号：US07550796B2
公开(公告)日：2009-06-23
申请号：US11947123
申请日：2007-11-29
申请人： Sang Hun Kim , Hyun Cheol Bae , Sang Heung Lee
发明人： Sang Hun Kim , Hyun Cheol Bae , Sang Heung Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66613 , H01L21/223 , H01L21/28079 , H01L29/165 , H01L29/41783 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66606 , H01L29/66742 , H01L29/78 , H01L29/78684
摘要： A germanium semiconductor device and a method of manufacturing the same are provided. The method includes the steps of: forming an isolation layer on a substrate using a shallow trench; forming a silicon-nitride layer on the substrate, and selectively etching the silicon nitride layer to expose source and drain regions; injecting impurities onto a surface of the substrate over the exposed source and drain regions using delta-doping to form a delta-doping layer; selectively growing a silicon germanium layer containing impurities on the delta-doping layer; rapidly annealing the substrate and forming source and drain regions by diffusion of the impurities; depositing an insulating layer on the entire surface of the substrate; etching the insulating layer and forming source and drain contact parts to be in contact with source and drain terminals; depositing metal over the insulating layer having the source and drain contact parts thereon and forming a metal silicide layer; and after forming the silicide layer, forming the source and drain terminals to be in contact with the silicide layer. Accordingly, the source and drain regions having a shallow junction depth may be ensured by forming the source and drain regions through annealing after delta-doping and selectively growing the silicon germanium layer containing high-concentration impurities. Also, the germanium silicide layer is stably formed by the silicon germanium layer grown in the source and drain regions, and thus contact resistance is lowered and driving current of the device is improved.
摘要翻译：提供锗半导体器件及其制造方法。该方法包括以下步骤：使用浅沟槽在衬底上形成隔离层; 在衬底上形成氮化硅层，并选择性地蚀刻氮化硅层以暴露出源区和漏区; 使用增量掺杂在暴露的源极和漏极区域上在衬底的表面上注入杂质以形成δ-掺杂层; 在δ-掺杂层上选择性地生长含有杂质的硅锗层; 快速退火衬底并通过杂质扩散形成源区和漏区; 在基板的整个表面上沉积绝缘层; 蚀刻绝缘层并形成源极和漏极接触部分以与源极和漏极端子接触; 在其上具有源极和漏极接触部分的绝缘层上沉积金属并形成金属硅化物层; 并且在形成硅化物层之后，形成与硅化物层接触的源极和漏极端子。因此，具有浅结深度的源极和漏极区域可以通过在增量掺杂之后退火形成源区和漏极区域并选择性地生长含有高浓度杂质的硅锗层来确保。此外，通过在源极区和漏极区中生长的硅锗层稳定地形成硅化锗层，因此接触电阻降低，器件的驱动电流提高。

6. 发明申请

US20090134944A1 CAPACITIVE-DEGENERATION DOUBLE CROSS-COUPLED VOLTAGE-CONTROLLED OSCILLATOR 有权
标题翻译：电容式变压器双相交流电压控制振荡器
公开(公告)号：US20090134944A1
公开(公告)日：2009-05-28
申请号：US12114705
申请日：2008-05-02
申请人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H03B5/12
CPC分类号： H03B5/1231 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1253
摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.
摘要翻译：提供电容变性双交叉耦合压控振荡器。电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容以增加主交叉振荡单元的负电阻。因此，可以增加最大可获得的振荡频率并降低输入电容。

7. 发明授权

US07902930B2 Colpitts quadrature voltage controlled oscillator 失效
标题翻译： Colpitts正交压控振荡器
公开(公告)号：US07902930B2
公开(公告)日：2011-03-08
申请号：US11927957
申请日：2007-10-30
申请人： Ja Yol Lee , Sang Heung Lee , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hyun Kyu Yu
IPC分类号： H03K3/03
CPC分类号： H03B5/1218 , H03B5/1231 , H03B2200/0074 , H03B2200/0078
摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.
摘要翻译：提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器可以实现。

8. 发明申请

US20080129392A1 COLPITTS QUADRATURE VOLTAGE CONTROLLED OSCILLATOR 失效
标题翻译： COLPITTS QUADRATURE电压控制振荡器
公开(公告)号：US20080129392A1
公开(公告)日：2008-06-05
申请号：US11927957
申请日：2007-10-30
申请人： Ja Yol Lee , Sang Heung Lee , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hyun Kyu Yu
IPC分类号： H03B27/00 , H03B5/12
CPC分类号： H03B5/1218 , H03B5/1231 , H03B2200/0074 , H03B2200/0078
摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.
摘要翻译：提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器可以实现。

9. 发明授权

US07852165B2 Capacitive-degeneration double cross-coupled voltage-controlled oscillator 有权
标题翻译：电容变性双交叉电压控制振荡器
公开(公告)号：US07852165B2
公开(公告)日：2010-12-14
申请号：US12114705
申请日：2008-05-02
申请人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H03B5/12
CPC分类号： H03B5/1231 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1253
摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.
摘要翻译：提供电容变性双交叉耦合压控振荡器。电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容以增加主交叉振荡单元的负电阻。因此，可以增加最大可获得的振荡频率并降低输入电容。

10. 发明授权

US07666749B2 SiGe semiconductor device and method of manufacturing the same 失效
标题翻译： SiGe半导体器件及其制造方法
公开(公告)号：US07666749B2
公开(公告)日：2010-02-23
申请号：US11947098
申请日：2007-11-29
申请人： Sang Hun Kim , Hyun Cheol Bae , Sang Heung Lee
发明人： Sang Hun Kim , Hyun Cheol Bae , Sang Heung Lee
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active region and a collector electrode region by forming a Si epitaxial layer on the substrate having the buried collector; forming an isolation layer on the substrate and exposing the collector layer and the collector electrode region; forming a collector pad oxide layer on the collector electrode region; stacking a base epitaxial layer and a pad oxide layer on the substrate having the collector pad oxide layer and patterning the pad oxide layer; forming a first polycrystalline Si (poly-Si) layer on the patterned pad oxide layer; exposing at least a portion of the patterned pad oxide layer by etching the first poly-Si layer; depositing a metal layer on the first poly-Si layer to form a first silicide layer; forming an oxide layer on the substrate having the first silicide layer, and exposing a base-emitter junction and the collector electrode region; forming an emitter electrode and a collector electrode by depositing a second poly-Si layer on the exposed base-emitter junction and collector electrode region; and depositing a metal layer on the emitter and collector electrodes to form a second silicide layer, and forming a base terminal, an emitter terminal, and a collector terminal. In this method, base parasitic resistance can be reduced, an electrical short due to agglomeration caused by Ge can be prevented during the formation of the silicide layer, and the base-emitter junction can be protected using the pad oxide layer from external processes, thereby enhancing process stability and reliability.
摘要翻译：提供了一种SiGe半导体器件及其制造方法。该方法包括以下步骤：通过将杂质离子掺杂到形成在衬底上的掩埋集电区中来形成掩埋集电极; 通过在具有该埋设集电体的基板上形成Si外延层，形成作为有源区和集电极区的集电极层; 在所述基板上形成隔离层并使所述集电极层和所述集电极区域露出; 在集电极区域上形成集电极氧化层; 在具有集电极衬垫氧化物层的衬底上堆叠基极外延层和焊盘氧化物层，并对衬垫氧化物层进行构图; 在所述图案化衬垫氧化物层上形成第一多晶Si（多晶硅）层; 通过蚀刻第一多晶硅层来暴露图案化的衬垫氧化物层的至少一部分; 在所述第一多晶硅层上沉积金属层以形成第一硅化物层; 在具有第一硅化物层的衬底上形成氧化物层，并暴露出基极 - 发射极结和集电极区域; 通过在暴露的基极 - 发射极结和集电极区域上沉积第二多晶硅层来形成发射极和集电极; 以及在所述发射极和集电极上沉积金属层以形成第二硅化物层，以及形成基极端子，发射极端子和集电极端子。在该方法中，可以降低基极寄生电阻，在硅化物层的形成期间可以防止由Ge引起的聚集引起的电短路，并且可以使用衬垫氧化物层从外部工艺来保护基极 - 发射极结，从而提高工艺稳定性和可靠性。

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