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1. 发明授权

US07451259B2 Method and apparatus for providing peer-to-peer data transfer within a computing environment 有权
标题翻译：用于在计算环境内提供对等数据传输的方法和装置
公开(公告)号：US07451259B2
公开(公告)日：2008-11-11
申请号：US11005451
申请日：2004-12-06
申请人： Samuel H. Duncan , Wei-Je Huang , John H. Edmondson
发明人： Samuel H. Duncan , Wei-Je Huang , John H. Edmondson
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9073
摘要： A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.
摘要翻译：一种用于通过互连结构提供对等数据传输的方法和装置。该方法和装置使得第一设备能够通过在互连结构上传递读取和写入请求来向/从第二设备的本地存储器读取和/或写入数据。即使当互连结构的通信协议不允许这样的传输时，也可以执行这种数据传送。

2. 发明授权

US07275123B2 Method and apparatus for providing peer-to-peer data transfer within a computing environment 有权
标题翻译：用于在计算环境内提供对等数据传输的方法和装置
公开(公告)号：US07275123B2
公开(公告)日：2007-09-25
申请号：US11005150
申请日：2004-12-06
申请人： Samuel H. Duncan , Wei-Je Huang , John H. Edmondson
发明人： Samuel H. Duncan , Wei-Je Huang , John H. Edmondson
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： H04L12/66
摘要： A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.
摘要翻译：一种用于通过互连结构提供对等数据传输的方法和装置。该方法和装置使得第一设备能够通过在互连结构上传递读取和写入请求来向/从第二设备的本地存储器读取和/或写入数据。即使当互连结构的通信协议不允许这样的传输时，也可以执行这种数据传送。

3. 发明授权

US08539130B2 Virtual channels for effective packet transfer 有权
标题翻译：用于有效数据包传输的虚拟通道
公开(公告)号：US08539130B2
公开(公告)日：2013-09-17
申请号：US12873057
申请日：2010-08-31
申请人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
发明人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
IPC分类号： G06F12/00 , G06F11/00
CPC分类号： G06F13/1605
摘要： The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.
摘要翻译：本发明提出了一种包括多个虚拟通道的交叉开关单元，每个虚拟通道是横杠单元内的逻辑数据流。耦合到源客户端子系统的仲裁逻辑被配置为基于源客户端子系统的类型和/或数据请求的类型来选择用于将数据请求或数据分组发送到目的地客户端子系统的虚拟信道。较高优先级的流量通过配置为传输数据而不引起死锁和/或停顿的虚拟通道进行传输。较低优先级的流量可以通过虚拟通道进行传输，可以停滞。

4. 发明申请

US20110072177A1 VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER 有权
标题翻译：用于有效分组传输的虚拟通道
公开(公告)号：US20110072177A1
公开(公告)日：2011-03-24
申请号：US12873057
申请日：2010-08-31
申请人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
发明人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F13/1605
摘要： The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.
摘要翻译：本发明提出了一种包括多个虚拟通道的交叉开关单元，每个虚拟通道是横杠单元内的逻辑数据流。耦合到源客户端子系统的仲裁逻辑被配置为基于源客户端子系统的类型和/或数据请求的类型来选择用于将数据请求或数据分组发送到目的地客户端子系统的虚拟信道。较高优先级的流量通过配置为传输数据而不引起死锁和/或停顿的虚拟通道进行传输。较低优先级的流量可以通过虚拟通道进行传输，可以停滞。

5. 发明申请

US20130311999A1 RESOURCE MANAGEMENT SUBSYSTEM THAT MAINTAINS FAIRNESS AND ORDER 有权
标题翻译：资源管理子系统维护公平和秩序
公开(公告)号：US20130311999A1
公开(公告)日：2013-11-21
申请号：US13476791
申请日：2012-05-21
申请人： Michael FETTERMAN , Shirish Gadre , John H. Edmondson , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Rajeshwaran Selvanesan , Charles McCarver , Kevin Mitchell , Steven James Heinrich
发明人： Michael FETTERMAN , Shirish Gadre , John H. Edmondson , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Rajeshwaran Selvanesan , Charles McCarver , Kevin Mitchell , Steven James Heinrich
IPC分类号： G06F9/50
CPC分类号： G06F9/5011 , G06F2209/507
摘要： One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.
摘要翻译：本公开的一个实施例阐述了在与重放操作相关的公共资源访问请求的调度中维持公平性和顺序的有效方式。具体地说，流式多处理器（SM）包括配置成通过一个或多个执行周期调度访问请求的总顺序队列（TOQ）。访问请求被允许在需要时将共同资源分配给该请求来进行进展。在多个访问请求需要相同的公共资源的情况下，优先级被赋予较旧的访问请求。访问请求可能处于睡眠状态，等待某些公共资源的可用性。可以通过允许较旧的访问请求从较年轻的资源请求中窃取资源来避免死锁。所公开的技术的一个优点是较旧的公共资源访问请求不被重复阻止以通过较新的访问请求提前进展。

6. 发明授权

US08341358B1 System and method for cleaning dirty data in a cache via frame buffer logic 有权
标题翻译：通过帧缓冲区逻辑清理缓存中的脏数据的系统和方法
公开(公告)号：US08341358B1
公开(公告)日：2012-12-25
申请号：US12562989
申请日：2009-09-18
申请人： John H. Edmondson , James Roberts
发明人： John H. Edmondson , James Roberts
IPC分类号： G06F13/00
CPC分类号： G06F12/0846 , G06F12/0804
摘要： One embodiment of the invention sets forth a mechanism for efficiently write dirty data from the L2 cache to a DRAM. A dirty data notification, including a memory address of the dirty data, is transmitted by the L2 cache to a frame buffer logic when dirty data is stored in the L2 cache. The frame buffer logic uses a page-stream sorter to organize dirty data notifications based on the bank page associated with the memory addresses included in the dirty data notifications. The page-stream sorter includes multiple sets with entries that may be associated with different bank pages in the DRAM. The frame buffer logic transmits dirty data associated with an entry that has a maximum threshold of dirty data notifications to the DRAM. The frame buffer logic also transmits dirty data associated with the oldest entry when the number of entries in a set reaches a maximum threshold.
摘要翻译：本发明的一个实施例提出了一种用于将有害数据从L2高速缓存写入DRAM的机制。当脏数据存储在L2高速缓存中时，包含脏数据的存储器地址的脏数据通知由L2高速缓存发送到帧缓冲器逻辑。帧缓冲器逻辑使用页面流排序器来基于与包含在脏数据通知中的存储器地址相关联的存储体页来组织脏数据通知。页面流分类器包括具有与DRAM中的不同存储体页面相关联的条目的多个集合。帧缓冲器逻辑将具有与脏数据通知的最大阈值的条目相关联的脏数据发送到DRAM。当一组中的条目数达到最大阈值时，帧缓冲器逻辑还发送与最早条目相关联的脏数据。

7. 发明授权

US08131931B1 Configurable cache occupancy policy 有权
标题翻译：可配置缓存占用策略
公开(公告)号：US08131931B1
公开(公告)日：2012-03-06
申请号：US12256378
申请日：2008-10-22
申请人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
发明人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
IPC分类号： G06F12/00
CPC分类号： G06F12/121
摘要： One embodiment of the invention is a method for evicting data from an intermediary cache that includes the steps of receiving a command from a client, determining that there is a cache miss relative to the intermediary cache, identifying one or more cache lines within the intermediary cache to store data associated with the command, determining whether any of data residing in the one or more cache lines includes raster operations data or normal data, and causing the data residing in the one or more cache lines to be evicted or stalling the command based, at least in part, on whether the data includes raster operations data or normal data. Advantageously, the method allows a series of cache eviction policies based on how cached data is categorized and the eviction classes of the data. Consequently, more optimized eviction decisions may be made, leading to fewer command stalls and improved performance.
摘要翻译：本发明的一个实施例是一种用于从中间缓存中取出数据的方法，包括以下步骤：从客户机接收命令，确定相对于中间缓存存在高速缓存未命中，识别中间缓存内的一个或多个高速缓存行存储与所述命令相关联的数据，确定驻留在所述一个或多个高速缓存行中的数据中的任何一个是否包括光栅操作数据或正常数据，以及使驻留在所述一个或多个高速缓存行中的数据被驱逐或停止所述命令，至少部分地关于数据是否包括光栅操作数据或正常数据。有利地，该方法允许基于缓存数据被分类和数据的逐出类别的一系列缓存驱逐策略。因此，可以进行更优化的驱逐决定，导致更少的命令停顿和改进的性能。

8. 发明授权

US08060700B1 System, method and frame buffer logic for evicting dirty data from a cache using counters and data types 有权
标题翻译：使用计数器和数据类型从缓存中排除脏数据的系统，方法和帧缓冲区逻辑
公开(公告)号：US08060700B1
公开(公告)日：2011-11-15
申请号：US12330469
申请日：2008-12-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
IPC分类号： G06F13/00 , G06F12/12
CPC分类号： G06F12/126 , G06F12/0804 , G06F2212/302
摘要： A system and method for cleaning dirty data in an intermediate cache are disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
摘要翻译：公开了一种用于清除中间缓存中的脏数据的系统和方法。当脏数据存储在L2高速缓存中时，包含存储器地址和数据类的脏数据通知由级别2（L2）高速缓存发送到帧缓冲器逻辑。数据类包括先驱逐出，最后逐出。在一个实施例中，属于第一数据类别的数据是具有很少重用潜力的光栅操作数据。帧缓冲器逻辑使用通知排序器来组织脏数据通知，其中通知分类器中的条目存储DRAM存储体页面编号，具有驻留脏数据的高速缓存行的第一计数和具有居民驱逐器的第一高速缓存行计数与该DRAM库相关联的脏数据。当第一个计数达到阈值时，帧缓冲器逻辑发送与条目相关联的脏数据。

9. 发明授权

US07805587B1 Memory addressing controlled by PTE fields 有权
标题翻译：由PTE字段控制的存储器寻址
公开(公告)号：US07805587B1
公开(公告)日：2010-09-28
申请号：US11555628
申请日：2006-11-01
申请人： James M. Van Dyke , John H. Edmondson
发明人： James M. Van Dyke , John H. Edmondson
IPC分类号： G06F9/34 , G06F12/00
CPC分类号： G06F12/10 , G06F12/0607
摘要： Embodiments of the present invention enable virtual-to-physical memory address translation using optimized bank and partition interleave patterns to improve memory bandwidth by distributing data accesses over multiple banks and multiple partitions. Each virtual page has a corresponding page table entry that specifies the physical address of the virtual page in linear physical address space. The page table entry also includes a data kind field that is used to guide and optimize the mapping process from the linear physical address space to the DRAM physical address space, which is used to directly access one or more DRAM. The DRAM physical address space includes a row, bank and column address. The data kind field is also used to optimize the starting partition number and partition interleave pattern that defines the organization of the selected physical page of memory within the DRAM memory system.
摘要翻译：本发明的实施例使得能够使用优化的存储体和分区交织模式进行虚拟到物理存储器地址转换，以通过在多个存储体和多个分区上分配数据访问来提高存储器带宽。每个虚拟页面都有一个对应的页表项，它指定了线性物理地址空间中的虚拟页面的物理地址。页表条目还包括数据类型字段，用于引导和优化从线性物理地址空间到用于直接访问一个或多个DRAM的DRAM物理地址空间的映射处理。 DRAM物理地址空间包括一行，一行和一列地址。数据类型字段还用于优化起始分区号和分区交织模式，其定义DRAM存储器系统内存储器的选定物理页面的组织。

10. 发明授权

US07620793B1 Mapping memory partitions to virtual memory pages 有权
标题翻译：将内存分区映射到虚拟内存页面
公开(公告)号：US07620793B1
公开(公告)日：2009-11-17
申请号：US11467679
申请日：2006-08-28
申请人： John H. Edmondson , Henry P. Moreton
发明人： John H. Edmondson , Henry P. Moreton
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00 , G06F12/06 , G06F13/28 , G06T11/40
CPC分类号： G06T1/60 , G06F12/0607 , G06F12/10 , G06F12/1009 , G06F2212/652
摘要： Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.
摘要翻译：使用非二功能虚拟内存页大小寻址内存的系统和方法通过在渲染过程中分配图形数据进行高效访问来提高图形内存带宽。可以为每个虚拟存储器页面选择各种分段步长，以修改映射到每个物理存储器分区的顺序地址的数量并改变交织粒度。寻址方案允许修改每个虚拟存储器页面的存储体交织模式以减少存储体冲突并提高存储器带宽利用率。寻址方案还允许修改每个虚拟存储器页面的分区交织模式以分布多个分区之间的访问并提高存储器带宽利用率。

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