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1. 发明授权

US06826653B2 Block data mover adapted to contain faults in a partitioned multiprocessor system 有权
标题翻译：阻止数据移动器适于在分区多处理器系统中包含故障
公开(公告)号：US06826653B2
公开(公告)日：2004-11-30
申请号：US10068427
申请日：2002-02-06
申请人： Samuel H. Duncan , Frederick C. Canter , Darrel D. Donaldson , David W. Hartwell
发明人： Samuel H. Duncan , Frederick C. Canter , Darrel D. Donaldson , David W. Hartwell
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/621
摘要： A system and method are provided for moving information between cache coherent memory systems of a partitioned multiprocessor computer system while containing faults to a single partition. The multiprocessor computer system includes a plurality of processors, memory subsystems and input/output (I/O) subsystems that can be divided into a plurality of partitions. Each I/O subsystem includes at least one I/O bridge for interfacing between one or more I/O devices and the multiprocessor system. The I/O bridge has a data mover configured to retrieve information from a “source” partition and to store that information within its own “destination” partition. When activated, the data mover issues a request to the source partition for a non-coherent copy of the information. The home memory subsystem in the source partition preferably responds to the request by sending the data mover “valid”, but non-coherent copy of the information, e.g., a “snapshot” of the information as of the time of the request. Upon receiving the information, the data mover may copy it into the memory subsystem of the destination partition.
摘要翻译：提供了一种系统和方法，用于在分区多处理器计算机系统的高速缓存一致存储器系统之间移动信息，同时将故障包含在单个分区中。多处理器计算机系统包括可以被分成多个分区的多个处理器，存储器子系统和输入/输出（I / O）子系统。每个I / O子系统包括用于在一个或多个I / O设备和多处理器系统之间进行接口的至少一个I / O桥。 I / O网桥具有数据移动设备，用于从“源”分区检索信息，并将该信息存储在其自己的“目标”分区中。当激活时，数据移动器向源分区发出请求，以获得不相干的信息副本。源分区中的家用存储器子系统优选地通过发送数据移动器“有效”但是信息的非相干副本（例如，请求的时间的信息的“快照”）来响应该请求。一旦接收到该信息，数据移动器可将其复制到目的地分区的存储子系统中。

2. 发明授权

US06920516B2 Anti-starvation interrupt protocol 有权
标题翻译：抗饥饿中断协议
公开(公告)号：US06920516B2
公开(公告)日：2005-07-19
申请号：US09944516
申请日：2001-08-31
申请人： David W. Hartwell , Samuel H. Duncan , David T. Mayo , David J. Golden
发明人： David W. Hartwell , Samuel H. Duncan , David T. Mayo , David J. Golden
IPC分类号： G06F13/24 , G06F13/40 , H03K5/19
CPC分类号： H03K5/19 , G06F13/24 , G06F13/4081 , G06F2213/2402
摘要： An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction. If it does, the interrupt controller issues a write transaction having a higher priority to the second CSR. In response, the processor copies all of the pending interrupts from the first CSR into the memory subsystem, thereby freeing up the first CSR to accept additional write transactions.
摘要翻译：提供了一种用于避免多处理器计算机系统中的活动锁定的反饥饿中断协议。至少一个处理器被配置为包括第一和第二控制状态寄存器（CSR）。第一个CSR缓冲器由处理器接收到的中断信息，而第二个CSR跟踪中断的优先级。当中断控制器接收到中断时，它会在处理器发出写入事务给第一个CSR。如果第一个CSR有空间接受写入事务，则处理器返回确认，而如果第一个CSR已经满，则处理器返回一个无确认。响应于无应答，中断控制器增加中断饥饿计数器，并检查计数器是否超过阈值。如果没有，则中断控制器等待预设时间并转发写入事务。如果是这样，中断控制器向第二个CSR发出具有较高优先级的写入事务。作为响应，处理器将来自第一CSR的所有待处理中断复制到存储器子系统中，从而释放第一个CSR以接受额外的写事务。

3. 发明授权

US08364851B2 Scalable efficient I/O port protocol 有权
标题翻译：可扩展的高效I / O端口协议
公开(公告)号：US08364851B2
公开(公告)日：2013-01-29
申请号：US10677583
申请日：2003-10-02
申请人： Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
发明人： Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
IPC分类号： G06F3/00
CPC分类号： G06F15/17381 , G06F12/0817 , G06F2212/621
摘要： A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.
摘要翻译：公开了一种支持高性能，可扩展和高效的I / O端口协议来连接到I / O设备的系统。分布式多处理计算机系统包含多个处理器，每个处理器都耦合到实现I / O端口协议的I / O桥ASIC。一个或多个I / O设备耦合到I / O桥ASIC，每个I / O设备能够通过发送和接收消息分组来访问计算机系统中的机器资源。计算机系统中的机器资源包括数据块，寄存器和中断队列。计算机系统中的每个处理器耦合到能够存储处理器之间共享的数据块的存储器模块。使用基于目录的一致性协议来维护该共享存储器系统中的共享数据块的一致性。使用与存储系统相同的一致性协议来维护I / O设备读写访问期间传输的数据块的一致性。只有当I / O桥ASIC具有数据块的排他副本时，I / O桥ASIC才能缓存在I / O设备读或写访问期间传输的数据块。 I / O桥ASIC包括支持数据块的顺序和无序DMA读和写数据流的DMA设备。由DMA设备执行的数据块的顺序读取流总是导致DMA设备接收不必写入存储器模块的相干数据块。

4. 发明授权

US06738836B1 Scalable efficient I/O port protocol 有权
标题翻译：可扩展的高效I / O端口协议
公开(公告)号：US06738836B1
公开(公告)日：2004-05-18
申请号：US09652391
申请日：2000-08-31
申请人： Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
发明人： Richard E. Kessler , Samuel H. Duncan , David W. Hartwell , David A. J. Webb, Jr. , Steve Lang
IPC分类号： G06F1300
CPC分类号： G06F15/17381 , G06F12/0817 , G06F2212/621
摘要： A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.
摘要翻译：公开了一种支持高性能，可扩展和高效的I / O端口协议来连接到I / O设备的系统。分布式多处理计算机系统包含多个处理器，每个处理器都耦合到实现I / O端口协议的I / O桥ASIC。一个或多个I / O设备耦合到I / O桥ASIC，每个I / O设备能够通过发送和接收消息分组来访问计算机系统中的机器资源。计算机系统中的机器资源包括数据块，寄存器和中断队列。计算机系统中的每个处理器耦合到能够存储处理器之间共享的数据块的存储器模块。使用基于目录的一致性协议来维护该共享存储器系统中的共享数据块的一致性。使用与存储系统相同的一致性协议来维护I / O设备读写访问期间传输的数据块的一致性。只有当I / O桥ASIC具有数据块的排他副本时，I / O桥ASIC才能缓存在I / O设备读或写访问期间传输的数据块。 I / O桥ASIC包括支持数据块的顺序和无序DMA读和写数据流的DMA设备。由DMA设备执行的数据块的顺序读取流总是导致DMA设备接收不必写入存储器模块的相干数据块。

5. 发明授权

US06701387B1 Adaptive data fetch prediction algorithm 有权
标题翻译：自适应数据提取预测算法
公开(公告)号：US06701387B1
公开(公告)日：2004-03-02
申请号：US09652644
申请日：2000-08-31
申请人： Roger Pannel , David W. Hartwell , Samuel H. Duncan , Rajen Ramchandani , Andrej Kocev , Jeffrey Willcox , Steven Ho
发明人： Roger Pannel , David W. Hartwell , Samuel H. Duncan , Rajen Ramchandani , Andrej Kocev , Jeffrey Willcox , Steven Ho
IPC分类号： G06F1300
CPC分类号： G06F12/0862 , G06F13/28
摘要： A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.
摘要翻译：一种用于通过DMA连接到多处理器系统网格的PCI协议I / O设备来适应DMA读请求的速度要求的方法和装置。描述了设备控制器和网格之间的桥接器，其将来自数据的数据的缓存行中的数据从数据缓存到I / O设备。该系统是自适应的，因为过去读取中所需的高速缓存行的数量被记住并用于确定高速缓存行的数量是减少还是增加。

6. 发明授权

US4979097A Method and apparatus for interconnecting busses in a multibus computer system 失效
标题翻译：在多机电脑系统中互连母线的方法和装置
公开(公告)号：US4979097A
公开(公告)日：1990-12-18
申请号：US93479
申请日：1987-09-04
申请人： Victoria M. Triolo , Elbert Bloom , David W. Hartwell
发明人： Victoria M. Triolo , Elbert Bloom , David W. Hartwell
IPC分类号： G06F13/36 , G06F5/06 , G06F13/40 , G06F13/42
CPC分类号： G06F5/06 , G06F13/405 , G06F13/4226
摘要： A bus adapter connecting a high-speed pended bus to a slower speed non-pended bus includes a first module functioning as a node of the pended bus and a second module functioning as a node of the non-pended bus. An interconnect bus extends between the two modules. Control signals on the interconnect bus generated by the first module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the second module, which have a finite duration. Control signals on the interconnect bus generated by the first module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the second module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.
摘要翻译：将高速挂起总线连接到较慢速度的非挂起总线的总线适配器包括用作挂起总线的节点的第一模块和用作非挂起总线的节点的第二模块。互连总线在两个模块之间延伸。由第一模块产生的互连总线上的控制信号包括具有不确定断言持续时间的状态信号，并且仅响应于由具有有限持续时间的第二模块产生的互连总线上的控制信号而被解除置位。由第一模块产生的互连总线上的控制信号由由等级不等式总线的时钟信号导出的多相时钟信号的两相控制的双等级同步器同步。由第二模块产生的互连总线上的控制信号由双级同步器同步，双等级同步器由从有争议的总线时钟信号导出的多相时钟信号的两相控制。

7. 发明授权

US08391022B2 Multi-function mezzanine board alignment and mounting device, with integrated handle 有权
标题翻译：多功能夹层板对位和安装装置，带集成手柄
公开(公告)号：US08391022B2
公开(公告)日：2013-03-05
申请号：US12043259
申请日：2008-03-06
申请人： Timothy W. Olesiewicz , David W. Hartwell , Brett C. Ong
发明人： Timothy W. Olesiewicz , David W. Hartwell , Brett C. Ong
IPC分类号： H05K7/02
CPC分类号： H05K7/20727
摘要： A mezzanine board alignment and mounting device includes a multi-stage pin connected to a main board near a mezzanine board connector disposed on the main board. The multistage pin includes a base adapted to connect to the main board, a point distal to the base adapted to pass through an opening on a mezzanine board, and a support disposed between the base and the point. A diameter of the point widens towards the support. A diameter of the support is wider than a diameter of the opening. When the point is fully inserted through the opening in the mezzanine board, the mezzanine board is aligned properly to connect with the mezzanine board connector on the main board.
摘要翻译：夹层板对准和安装装置包括连接到设置在主板上的夹层板连接器附近的主板的多级引脚。多级销包括适于连接到主板的底座，适于穿过夹层板上的开口的基座远侧的点，以及设置在基座和点之间的支撑件。点的直径朝向支撑件变宽。支撑件的直径比开口的直径宽。当夹点完全插入夹层板中的开口时，夹层板正确对齐，以连接主板上的夹层板连接器。

8. 发明授权

US4864496A Bus adapter module for interconnecting busses in a multibus computer system 失效
标题翻译：用于在多计算机系统中互连总线的总线适配器模块
公开(公告)号：US4864496A
公开(公告)日：1989-09-05
申请号：US93488
申请日：1987-09-04
申请人： Victoria M. Triolo , Elbert Bloom , David W. Hartwell
发明人： Victoria M. Triolo , Elbert Bloom , David W. Hartwell
IPC分类号： G06F13/40
CPC分类号： G06F13/405
摘要： A control adapter module in a bus adapter connecting a high-speed pended bus to a slower speed non-pended bus functions as a node of the non-pended bus. An interconnect bus extends between the control module and a response adapter module functioning as a node on the pended bus. Control signals on the interconnect bus generated by the response module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the control module, which have a finite duration. Control signals on the interconnect bus generated by the response module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the control module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.
摘要翻译：总线适配器中的控制适配器模块将高速挂起总线连接到较慢速度的非挂起总线，作为非挂起总线的节点。互连总线在控制模块和作为挂起总线上的节点的响应适配器模块之间延伸。由响应模块产生的互连总线上的控制信号包括具有不确定的断言持续时间的状态信号，并且仅响应于由具有有限持续时间的控制模块产生的互连总线上的控制信号而被解除置位。由响应模块生成的互连总线上的控制信号由双级同步器同步，该双级同步器由从非等效总线的时钟信号导出的多相时钟信号的两相控制。由控制模块生成的互连总线上的控制信号由双级同步器同步，该双级同步器由从有争议的总线时钟信号导出的多相时钟信号的两相控制。

9. 发明申请

US20090225527A1 MULTI-FUNCTION MEZZANINE BOARD ALIGNMENT AND MOUNTING DEVICE, WITH INTEGRATED HANDLE 有权
标题翻译：多功能MEZZANINE BOARD对准和安装设备，带集成手柄
公开(公告)号：US20090225527A1
公开(公告)日：2009-09-10
申请号：US12043259
申请日：2008-03-06
申请人： Timothy W. Olesiewicz , David W. Hartwell , Brett C. Ong
发明人： Timothy W. Olesiewicz , David W. Hartwell , Brett C. Ong
IPC分类号： H05K7/14 , H05K1/11
CPC分类号： H05K7/20727
摘要： A mezzanine board alignment and mounting device includes a multi-stage pin connected to a main board near a mezzanine board connector disposed on the main board. The multistage pin includes a base adapted to connect to the main board, a point distal to the base adapted to pass through an opening on a mezzanine board, and a support disposed between the base and the point. A diameter of the point widens towards the support. A diameter of the support is wider than a diameter of the opening. When the point is fully inserted through the opening in the mezzanine board, the mezzanine board is aligned properly to connect with the mezzanine board connector on the main board.
摘要翻译：夹层板对准和安装装置包括连接到设置在主板上的夹层板连接器附近的主板的多级引脚。多级销包括适于连接到主板的底座，适于穿过夹层板上的开口的基座远侧的点，以及设置在基座和点之间的支撑件。点的直径朝向支撑件变宽。支撑件的直径比开口的直径宽。当夹点完全插入夹层板中的开口时，夹层板正确对齐，以连接主板上的夹层板连接器。

10. 发明授权

US07065169B2 Detection of added or missing forwarding data clock signals 失效
公开(公告)号：US07065169B2
公开(公告)日：2006-06-20
申请号：US09944500
申请日：2001-08-31
申请人： David W. Hartwell
发明人： David W. Hartwell
IPC分类号： H04L7/00
CPC分类号： H03K5/19 , G06F13/24 , G06F13/4081 , G06F2213/2402
摘要： A system is disclosed that detects data forwarding clock errors including both missing and additional clock signals. The system provides for a phase locked loop (PLL) that locks onto a data forwarding source synchronous clock signal wherein the PLL outputs a system clock whose frequency is the average of the data forwarding clock frequency. The data forwarding clock signals and the system clock signals are counted separately and when a discrepancy occurs the receiving system is informed that an error has occurred. The receiving system will handle the error in its routine fashion. The counters and the PLL are synchronized to be sure that the PLL has acquired a lock before the error detection is enabled.

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