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1. 发明申请

US20130015580A1 REPLACEMENT METAL GATE STRUCTURE AND METHODS OF MANUFACTURE 有权
标题翻译：替代金属门结构和制造方法
公开(公告)号：US20130015580A1
公开(公告)日：2013-01-17
申请号：US13180842
申请日：2011-07-12
申请人： SAMEER H JAIN , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
发明人： SAMEER H JAIN , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28167 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material.
摘要翻译：提供替代的金属栅极结构及其制造方法。所述方法包括形成至少一个沟槽结构并在所述至少一个沟槽结构中形成高k电介质材料的衬垫。该方法还包括调整高k电介质材料的衬垫的高度。所述方法还包括在所述衬垫上形成至少一个功函数金属，以及在所述至少一个功函数金属和所述高k电介质材料的衬垫上，在所述至少一个沟槽结构中形成金属栅极结构。

2. 发明授权

US08642424B2 Replacement metal gate structure and methods of manufacture 有权
标题翻译：替代金属门结构及其制造方法
公开(公告)号：US08642424B2
公开(公告)日：2014-02-04
申请号：US13180842
申请日：2011-07-12
申请人： Sameer H. Jain , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
发明人： Sameer H. Jain , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28167 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material.
摘要翻译：提供替代的金属栅极结构及其制造方法。所述方法包括形成至少一个沟槽结构并在所述至少一个沟槽结构中形成高k电介质材料的衬垫。该方法还包括调整高k电介质材料的衬垫的高度。所述方法还包括在所述衬垫上形成至少一个功函数金属，以及在所述至少一个功函数金属和所述高k电介质材料的衬垫上，在所述至少一个沟槽结构中形成金属栅极结构。

3. 发明授权

US08741725B2 Butted SOI junction isolation structures and devices and method of fabrication 有权
标题翻译：对接SOI结隔离结构和器件及其制造方法
公开(公告)号：US08741725B2
公开(公告)日：2014-06-03
申请号：US12943084
申请日：2010-11-10
申请人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
发明人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
IPC分类号： H01L29/06
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

4. 发明申请

US20120112280A1 BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 有权
标题翻译：所谓的SOI结隔离结构和装置以及制造方法
公开(公告)号：US20120112280A1
公开(公告)日：2012-05-10
申请号：US12943084
申请日：2010-11-10
申请人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
发明人： Jeffrey B. Johnson , Shreesh Narasimha , Hasan M. Nayfeh , Viorel Ontalus , Robert R. Robison
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

5. 发明授权

US08017483B2 Method of creating asymmetric field-effect-transistors 有权
标题翻译：制造不对称场效应晶体管的方法
公开(公告)号：US08017483B2
公开(公告)日：2011-09-13
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对与基底垂直。

6. 发明申请

US20110089499A1 STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES 有权
公开(公告)号：US20110089499A1
公开(公告)日：2011-04-21
申请号：US12581924
申请日：2009-10-20
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

7. 发明授权

US07659172B2 Structure and method for reducing miller capacitance in field effect transistors 失效
标题翻译：用于减小场效应晶体管中的铣刀电容的结构和方法
公开(公告)号：US07659172B2
公开(公告)日：2010-02-09
申请号：US11164343
申请日：2005-11-18
申请人： Hasan M. Nayfeh , Andrew Waite
发明人： Hasan M. Nayfeh , Andrew Waite
IPC分类号： H01L21/336
CPC分类号： H01L29/78639 , H01L29/458 , H01L29/66772
摘要： A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.
摘要翻译：一种用于形成场效应晶体管（FET）器件的方法包括在半导体晶片的有源器件区域上形成栅极导体和栅极电介质，所述半导体晶片包括形成于体基板上的掩埋绝缘体层和绝缘体上半导体层最初形成在掩埋绝缘体层上。源极和漏极延伸部分形成在绝缘体上半导体层中，栅极导体的相邻相对侧，源极和漏极侧壁间隔物邻近栅极导体形成。绝缘体上半导体层的邻近侧壁间隔物的剩余部分被去除，以便露出掩埋绝缘体层的部分。去除掩埋绝缘体层的暴露部分以暴露本体衬底的部分。外延生长在体基板和源极和漏极延伸部分的暴露部分上的半导体层，并且在外延生长层中形成源极和漏极注入。

8. 发明申请

US20080121931A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080121931A1
公开(公告)日：2008-05-29
申请号：US11468403
申请日：2006-08-30
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

9. 发明申请

US20120217585A1 Structure and Method for Manufacturing Asymmetric Devices 有权
标题翻译：制造不对称设备的结构和方法
公开(公告)号：US20120217585A1
公开(公告)日：2012-08-30
申请号：US13468270
申请日：2012-05-10
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L27/088
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

10. 发明授权

US08232151B2 Structure and method for manufacturing asymmetric devices 有权
标题翻译：用于制造不对称装置的结构和方法
公开(公告)号：US08232151B2
公开(公告)日：2012-07-31
申请号：US13167303
申请日：2011-06-23
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

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