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1. 发明授权

US5258377A 2-spirocyclopropyl 4-acylcephems 失效
标题翻译： 2-螺环丙基4-酰基鞘
公开(公告)号：US5258377A
公开(公告)日：1993-11-02
申请号：US681680
申请日：1991-04-08
申请人： Samarendra N. Maiti , Narender A. V. Reddy , David Czajkowski , Paul Spevak , Charles Fiakpui , Ronald G. Micetich
发明人： Samarendra N. Maiti , Narender A. V. Reddy , David Czajkowski , Paul Spevak , Charles Fiakpui , Ronald G. Micetich
IPC分类号： A61K31/545 , A61K31/546 , A61P11/00 , A61P19/06 , A61P29/00 , C07D501/00 , C07D501/62 , C07D501/57
CPC分类号： C07D501/00
摘要： Derivatives of 2-spirocyclopropyl 4-acylcephem sulfones of the formula (I) ##STR1## are provided which are useful as potent elastase inhibitors and hence are useful in the prevention, control and treatment of inflammatory conditions, especially arthritis and emphysema.
摘要翻译：提供式（I）的2-螺环丙基4-酰基头孢烯砜的衍生物（I），其可用作有效的弹性蛋白酶抑制剂，因此可用于预防，控制和治疗炎性病症，特别是关节炎和肺气肿。

2. 发明授权

US5264430A 2-spirocyclopropyl cephalosporin sulfone derivatives 失效
标题翻译： 2-螺环丙基头孢菌素砜衍生物
公开(公告)号：US5264430A
公开(公告)日：1993-11-23
申请号：US685960
申请日：1991-04-08
申请人： Samarendra N. Maiti , David Czajkowski , Paul Spevak , Kazuo Adachi , Ronald G. Micetich
发明人： Samarendra N. Maiti , David Czajkowski , Paul Spevak , Kazuo Adachi , Ronald G. Micetich
IPC分类号： A61K31/545 , A61K31/546 , A61P11/00 , A61P29/00 , A61P43/00 , C07D501/00 , C07D501/04 , C07D501/08 , C07D501/10 , C07D501/14 , C07D501/18 , C07D501/62 , C07D501/20
CPC分类号： C07D501/00
摘要： Derivatives of 2-spirocyclopropyl cephalosporin sulfone of the structural formula I ##STR1## are provided which are useful as potent elastase inhibitors.
摘要翻译：提供了结构式I的2-螺环丙基头孢菌素砜的衍生物，其可用作有效的弹性蛋白酶抑制剂。

3. 发明授权

US5264429A 2-spirocyclopropyl cephalosporin sulfone derivatives 失效
公开(公告)号：US5264429A
公开(公告)日：1993-11-23
申请号：US747762
申请日：1991-08-20
申请人： Samarendra N. Maiti , David Czajkowski , Paul Spevak , Kazuo Adachi , Ronald G. Micetich
发明人： Samarendra N. Maiti , David Czajkowski , Paul Spevak , Kazuo Adachi , Ronald G. Micetich
IPC分类号： A61K31/545 , A61K31/546 , C07D501/00 , C07D501/62
CPC分类号： C07D501/00
摘要： Derivatives of 2-spirocyclopropyl cephalosporin sulfone of the structural formula I ##STR1## are provided which are useful as potent elastase inhibitors.

4. 发明授权

US5446037A 2-[(substituted) methylene]cephalosporin sulfones as antiinflammatory, antidegenerative and antithrombin agents 失效
标题翻译： 2 - [（取代的）亚甲基]头孢菌素砜作为抗炎，抗代谢和抗凝血酶剂
公开(公告)号：US5446037A
公开(公告)日：1995-08-29
申请号：US165576
申请日：1993-12-13
申请人： Samarendra Maiti , Charles Fiakpui , A. V. N. Reddy , David Czajkowski , Paul Spevak , Harninder Atwal , Ronald G. Micetich
发明人： Samarendra Maiti , Charles Fiakpui , A. V. N. Reddy , David Czajkowski , Paul Spevak , Harninder Atwal , Ronald G. Micetich
IPC分类号： C07D501/00 , C07D501/20 , A61K31/545
CPC分类号： C07D501/00
摘要： This invention relates to 2-[(substituted)methylene]cephalosporin sulfones and in particular 2-[(heteroaryl substituted)methylene]cephalosporin sulfones which are effective elastase inhibitors as well as effective thrombin inhibitors and therefore are useful as anti-inflammatory, anti-degenerative and anti-thrombin agents.
摘要翻译：本发明涉及2 - [（取代的）亚甲基]头孢菌素砜，特别是2 - [（杂芳基取代的）亚甲基]头孢菌素砜，它们是有效的弹性蛋白酶抑制剂以及有效的凝血酶抑制剂，因此可用作抗炎，退行性和抗凝血酶剂。

5. 发明授权

US07100048B1 Encrypted internet and intranet communication device 失效
标题翻译：加密互联网和内联网通信设备
公开(公告)号：US07100048B1
公开(公告)日：2006-08-29
申请号：US09490941
申请日：2000-01-25
申请人： David Czajkowski , Bernard Gudaitis
发明人： David Czajkowski , Bernard Gudaitis
IPC分类号： G06F1/24
CPC分类号： H04L63/0428 , H04L51/00 , H04L63/0823 , H04L63/083 , H04L63/123
摘要： A method and apparatus for providing multiple layer encrypted Internet, Intranet, or e-mail communication device communications. In particular, the process of encrypting Internet, Intranet, or e-mail messages with encryption algorithms embedded in integrated circuits incorporated into the communication device, with access to the encrypting circuit requiring a validation of a randomly generated cypher key and an user defined password.
摘要翻译：一种用于提供多层加密的因特网，内联网或电子邮件通信设备通信的方法和装置。特别地，利用嵌入到通信设备中的集成电路中的加密算法来加密因特网，内联网或电子邮件消息的过程，访问需要验证随机生成的密码密钥和用户定义密码的加密电路。

6. 发明授权

US07318169B2 Fault tolerant computer 有权
标题翻译：容错计算机
公开(公告)号：US07318169B2
公开(公告)日：2008-01-08
申请号：US10435626
申请日：2003-05-06
申请人： David Czajkowski
发明人： David Czajkowski
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3836 , G06F11/00 , G06F11/1479 , G06F11/1497 , G06F11/1695
摘要： A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).
摘要翻译：一种用于检测和校正由单一事件扰乱（SEU）的外部来源引起的计算机或微处理器中引起的错误或故障的新方法。这种方法被称为时间三重模块冗余（TTMR），并且基于这样的想法，即非常长的指令字（VLIW）风格的微处理器提供外部可控的并行计算元件，其可以用于组合时间冗余和空间冗余故障错误检测和校正技术该方法在单个微处理器中完成，代替传统的多处理器冗余技术，如三重模块冗余（TMR）。

7. 发明申请

US20070074046A1 Secure microprocessor and method 审中-公开
标题翻译：安全微处理器和方法
公开(公告)号：US20070074046A1
公开(公告)日：2007-03-29
申请号：US11366373
申请日：2006-03-03
申请人： David Czajkowski , Carl Murphy
发明人： David Czajkowski , Carl Murphy
IPC分类号： G06F12/14
CPC分类号： G06F21/75 , G06F21/14 , G06F21/72
摘要： A method and reconfigurable computer architecture protect binary opcode, or other data and instructions by providing an encryption capability integrated into an instruction issue unit of a protected processor. Opcodes are encrypted at their source, and encrypted opcodes are then delivered to the CPU and decrypted “inside” the CPU. Access into the CPU is prevented. Each form of code or data selected for protection is protected from unauthorized viewing or access. Commonly, the binary executable, or object, code is selected for protection. However, protected information could also include source code or data sets or both. Encrypting opcodes will result in making unique opcodes for each processor. Encryption keys and hidden opcode algorithms provide further security.
摘要翻译：一种方法和可重新配置的计算机体系结构通过提供集成到受保护处理器的指令发布单元中的加密功能来保护二进制操作码或其他数据和指令。操作码在其源处被加密，然后将加密的操作码传送到CPU并在“内部”中解密。阻止访问CPU。选择保护的每种形式的代码或数据都可以免受未经授权的查看或访问。通常，选择二进制可执行文件或对象代码进行保护。然而，受保护的信息也可以包括源代码或数据集或两者。加密操作码将导致为每个处理器独一无二的操作码。加密密钥和隐藏的操作码算法提供了进一步的安全性。

8. 发明申请

US20050055607A1 Functional interrupt mitigation for fault tolerant computer 有权
标题翻译：容错计算机的功能中断缓解
公开(公告)号：US20050055607A1
公开(公告)日：2005-03-10
申请号：US10656720
申请日：2003-09-08
申请人： David Czajkowski , Darrell Sellers
发明人： David Czajkowski , Darrell Sellers
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F11/00
摘要： A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs. This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).
摘要翻译：一种用于检测和校正由传播到微处理器的内部控制功能或电路的外部单事件故障源（SEU）引起的计算机或微处理器中引起的环境诱发功能中断（或“挂起”）的新方法。该方法被称为硬化核（或H-Core），并且基于添加到计算机系统中并连接到微处理器的环境硬化电路的添加，以在发生功能中断时向微处理器提供监视和中断或复位。硬化核心方法可以与用于检测和校正由外部源SEU引起的计算机或微处理器中引起的单位错误或故障的另一种方法相结合。这种方法被称为时间三重模块冗余（TTMR），并且基于这样的想法，即非常长的指令字（VLIW）风格的微处理器提供外部可控的并行计算元件，其可以用于组合时间冗余和空间冗余故障错误检测和校正技术该方法在单个微处理器中完成，代替传统的多处理器冗余技术，如三重模块冗余（TMR）。

9. 发明申请

US20050005203A1 SEU and SEFI fault tolerant computer 失效
标题翻译： SEU和SEFI容错计算机
公开(公告)号：US20050005203A1
公开(公告)日：2005-01-06
申请号：US10767477
申请日：2004-01-28
申请人： David Czajkowski
发明人： David Czajkowski
IPC分类号： H02H3/05
CPC分类号： G06F11/1497
摘要： A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.
摘要翻译：非硬化处理器对SEU和SEFI容错。提供了利用时间冗余来检测和响应于SEU的处理器。在辐射硬化模块中提供比较电路，以提供需要运行附加处理器的特殊冗余。此外，提供硬化的SEFI电路以周期性地向处理器发送信号，在处理器不处于SEFI状态的情况下，由处理器启动“正确”响应的生成。如果在特定时间窗口内没有收到正确的响应，则SEFI电路将启动逐步严重的操作，直到达到复位。

10. 发明授权

US6064555A Radiation induced single event latchup protection and recovery of integrated circuits 失效
标题翻译：辐射诱发单事件闭锁保护和集成电路的恢复
公开(公告)号：US6064555A
公开(公告)日：2000-05-16
申请号：US763153
申请日：1997-02-25
申请人： David Czajkowski , James C. Marshall
发明人： David Czajkowski , James C. Marshall
IPC分类号： H01L23/552 , H01L27/02 , H01L27/092 , H01L21/78
CPC分类号： H01L27/0921 , H01L23/552 , H01L27/0248 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L24/48 , H01L2924/00014 , H01L2924/12035 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195 , H01L2924/3025
摘要： An apparatus is disclosed for improving the Single Event Latchup (SEL) performance of an integrated circuit device (IC), or grouping of devices (as an example Multi-Chip Modules or MCMs), through the addition of active electronic circuitry integrated within the IC or MCM package. This circuitry and the protected device can be incorporated within the same physical dimensions and electrical configuration as the original integrated circuit device. The circuitry turns a destructive Latchup of a device into a recoverable event, allowing electronic devices that where unsuitable for the space environment due to SEL to be useable in the space environment.
摘要翻译：公开了一种用于通过添加集成在IC内的有源电子电路来改善集成电路器件（IC）的单事件锁存（SEL）性能或设备（例如多芯片模块或MCM）的分组）的装置或MCM包。该电路和受保护器件可以并入与原始集成电路器件相同的物理尺寸和电气配置。电路将设备的破坏性Latchup转换为可恢复事件，允许由于SEL而导致的空间环境不适合的电子设备在空间环境中可用。

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