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1. 发明授权

US08789172B2 Methods, media, and systems for detecting attack on a digital processing device 有权
标题翻译：用于检测对数字处理设备的攻击的方法，媒体和系统
公开(公告)号：US08789172B2
公开(公告)日：2014-07-22
申请号：US12406814
申请日：2009-03-18
申请人： Salvatore J. Stolfo , Wei-Jen Li , Angelos D. Keromylis , Elli Androulaki
发明人： Salvatore J. Stolfo , Wei-Jen Li , Angelos D. Keromylis , Elli Androulaki
IPC分类号： G06F11/00
CPC分类号： G06F21/50 , G06F21/56 , G06F21/562 , G06F21/566
摘要： Methods, media, and systems for detecting attack are provided. In some embodiments, the methods include: comparing at least part of a document to a static detection model; determining whether attacking code is included in the document based on the comparison of the document to the static detection model; executing at least part of the document; determining whether attacking code is included in the document based on the execution of the at least part of the document; and if attacking code is determined to be included in the document based on at least one of the comparison of the document to the static detection model and the execution of the at least part of the document, reporting the presence of an attack. In some embodiments, the methods include: selecting a data segment in at least one portion of an electronic document; determining whether the arbitrarily selected data segment can be altered without causing the electronic document to result in an error when processed by a corresponding program; in response to determining that the arbitrarily selected data segment can be altered, arbitrarily altering the data segment in the at least one portion of the electronic document to produce an altered electronic document; and determining whether the corresponding program produces an error state when the altered electronic document is processed by the corresponding program.
摘要翻译：提供了检测攻击的方法，媒体和系统。在一些实施例中，所述方法包括：将文档的至少一部分与静态检测模型进行比较; 基于文档与静态检测模型的比较来确定攻击代码是否包括在文档中; 执行文档的至少一部分; 基于所述文档的至少一部分的执行来确定所述文档中是否包含攻击代码; 并且如果基于文档与静态检测模型的比较和文档的至少部分的执行中的至少一个来确定攻击代码被包括在文档中，则报告攻击的存在。在一些实施例中，所述方法包括：在电子文档的至少一部分中选择数据段; 确定是否可以改变任意选择的数据段，而不会导致电子文档在由相应的程序处理时导致错误; 响应于确定可以改变任意选择的数据段，任意地更改电子文档的至少一部分中的数据段以产生改变的电子文档; 以及当所述改变的电子文档被相应的程序处理时，确定相应的程序是否产生错误状态。

2. 发明申请

US20100064369A1 METHODS, MEDIA, AND SYSTEMS FOR DETECTING ATTACK ON A DIGITAL PROCESSING DEVICE 有权
标题翻译：用于检测数字处理设备上的攻击的方法，媒体和系统
公开(公告)号：US20100064369A1
公开(公告)日：2010-03-11
申请号：US12406814
申请日：2009-03-18
申请人： Salvatore J. Stolfo , Wei-Jen Li , Angelos D. Keromylis , Elli Androulaki
发明人： Salvatore J. Stolfo , Wei-Jen Li , Angelos D. Keromylis , Elli Androulaki
IPC分类号： G06F21/00
CPC分类号： G06F21/50 , G06F21/56 , G06F21/562 , G06F21/566
摘要： Methods, media, and systems for detecting attack are provided. In some embodiments, the methods include: comparing at least part of a document to a static detection model; determining whether attacking code is included in the document based on the comparison of the document to the static detection model; executing at least part of the document; determining whether attacking code is included in the document based on the execution of the at least part of the document; and if attacking code is determined to be included in the document based on at least one of the comparison of the document to the static detection model and the execution of the at least part of the document, reporting the presence of an attack. In some embodiments, the methods include: selecting a data segment in at least one portion of an electronic document; determining whether the arbitrarily selected data segment can be altered without causing the electronic document to result in an error when processed by a corresponding program; in response to determining that the arbitrarily selected data segment can be altered, arbitrarily altering the data segment in the at least one portion of the electronic document to produce an altered electronic document; and determining whether the corresponding program produces an error state when the altered electronic document is processed by the corresponding program.
摘要翻译：提供了检测攻击的方法，媒体和系统。在一些实施例中，所述方法包括：将文档的至少一部分与静态检测模型进行比较; 基于文档与静态检测模型的比较来确定攻击代码是否包括在文档中; 执行文档的至少一部分; 基于所述文档的至少一部分的执行来确定所述文档中是否包含攻击代码; 并且如果基于文档与静态检测模型的比较和文档的至少部分的执行中的至少一个来确定攻击代码被包括在文档中，则报告攻击的存在。在一些实施例中，所述方法包括：在电子文档的至少一部分中选择数据段; 确定是否可以改变任意选择的数据段，而不会导致电子文档在由相应的程序处理时导致错误; 响应于确定可以改变任意选择的数据段，任意地更改电子文档的至少一部分中的数据段以产生改变的电子文档; 以及当所述改变的电子文档被相应的程序处理时，确定相应的程序是否产生错误状态。

3. 发明授权

US06934335B2 Video encoder with embedded scene change and 3:2 pull-down detections 有权
标题翻译：具有嵌入式场景变化和3：2下拉检测的视频编码器
公开(公告)号：US06934335B2
公开(公告)日：2005-08-23
申请号：US10014966
申请日：2001-12-11
申请人： Ming-Chang Liu , Wei-Jen Li , Ikuo Tsukagoshi
发明人： Ming-Chang Liu , Wei-Jen Li , Ikuo Tsukagoshi
IPC分类号： H04N5/14 , H04N7/01 , H04N7/26 , H04N7/50 , H04N7/12
CPC分类号： H04N5/147 , H04N5/145 , H04N7/0112 , H04N19/114 , H04N19/142 , H04N19/177 , H04N19/179 , H04N19/51 , H04N19/61 , H04N19/87
摘要： In one embodiment, a video encoder having a first and second phase of motion estimation, and scene change and 3:2 pull-down detection components is provided. In another embodiment, the first phase of motion estimation determines a set of field motion vectors to execute the scene change and 3:2 pull-down detection components. In another embodiment, the scene change and 3:2 pull-down detection component, and the second phase of the motion estimation occur after the first phase of motion estimation.
摘要翻译：在一个实施例中，提供具有运动估计的第一和第二相位以及场景变化和3：2下拉检测部件的视频编码器。在另一个实施例中，运动估计的第一阶段确定一组场运动矢量以执行场景变化和3：2下拉检测分量。在另一个实施例中，场景变化和3：2下拉检测分量以及运动估计的第二阶段在运动估计的第一阶段之后发生。

4. 发明授权

US06243728B1 Partitioned shift right logic circuit having rounding support 有权
标题翻译：具有四舍五入支持的分区右移逻辑电路
公开(公告)号：US06243728B1
公开(公告)日：2001-06-05
申请号：US09351273
申请日：1999-07-12
申请人： Aamir Alam Farooqui , Vojin G. Oklobdzija , Farzad Chehrazi , Wei-Jen Li , Andy W. Yu
发明人： Aamir Alam Farooqui , Vojin G. Oklobdzija , Farzad Chehrazi , Wei-Jen Li , Andy W. Yu
IPC分类号： G06F501
CPC分类号： G06F7/505 , G06F5/015 , G06F7/49947 , G06F7/49952
摘要： A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be accepted. The right shift circuit is partitioned so that the 32-bit value can represent: (1) a single 32-bit number; or (2) two 16-bit values. A 1 bit selection input indicates the particular partition format. In operation, if the input value is not negative, then one (“1”) is added at the guard bit position and a right shift with truncate is performed. If the input is negative and the guard bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is one, then one is added at the guard bit position and a right shift with truncate is performed. The shift circuitry used by the present invention is fully partitioned to accept word or half-word input and contains multiple cascaded multiplexer stages for performing partitioned right shifting and supports signed shifting. Each multiplexer stage can be programmed to perform a selected shift amount (including 0 shift). The right shift circuit of the present invention can be used in multi-media applications and can also be used for general purpose and VLIW (very long instruction word) processor without performance degradation.
摘要翻译：分配的右移逻辑电路，可编程并包含四舍五入支持。本发明的电路接受32位值和移位量，然后对32位执行右移操作，并自动舍入结果。可以接受签名或无符号值。右移位电路被分区，使得32位值可以表示为：（1）单个32位数; 或（2）两个16位值。 1位选择输入表示特定的分区格式。在操作中，如果输入值不为负，则在保护位位置添加一个（“1”），并执行具有截断的右移位。如果输入为负并且保护位为零，则不进行任何加法，并且执行具有截断的右移位。如果输入为负，保护位为1，粘滞位为零，则不进行加法，并执行带截断的右移位。如果输入为负并且保护位为1，粘滞位为1，则在保护位位置添加一个，并执行带有截断的右移位。本发明使用的移位电路被完全划分为接受字或半字输入，并且包含用于执行分区右移的多个级联多路复用器级并且支持符号移位。每个复用器级可以被编程以执行所选择的移位量（包括0移位）。本发明的右移位电路可用于多媒体应用，也可用于通用和VLIW（非常长的指令字）处理器，而不会降低性能。

5. 发明授权

US07203238B2 3:2 Pull-down detection 有权
标题翻译： 3：2下拉检测
公开(公告)号：US07203238B2
公开(公告)日：2007-04-10
申请号：US10014974
申请日：2001-12-11
申请人： Ming-Chang Liu , Wei-Jen Li , Ikuo Tsukagoshi
发明人： Ming-Chang Liu , Wei-Jen Li , Ikuo Tsukagoshi
IPC分类号： H04N7/12
CPC分类号： H04N5/147 , H04N5/145 , H04N7/0112 , H04N19/114 , H04N19/142 , H04N19/177 , H04N19/179 , H04N19/51 , H04N19/61 , H04N19/87
摘要： In one embodiment, a 3:2 pull-down detection component of a video encoder uses motion vectors to determine whether a repeated field exists in a video sequence. The 3:2 pull-down detection component uses field motion vectors determined by a motion estimator and compares the field motion vectors to a threshold to determine whether a repeated field exists. If a repeated field exists, a video encoder can then eliminate the repeated field.
摘要翻译：在一个实施例中，视频编码器的3：2下拉检测组件使用运动矢量来确定视频序列中是否存在重复的场。 3：2下拉检测组件使用由运动估计器确定的场运动矢量，并将场运动矢量与阈值进行比较，以确定是否存在重复场。如果存在重复的场，则视频编码器可以消除重复的场。

6. 发明授权

US06507614B1 Efficient de-quantization in a digital video decoding process using a dynamic quantization matrix for parallel computations 有权
标题翻译：在使用用于并行计算的动态量化矩阵的数字视频解码过程中的高效去量化
公开(公告)号：US06507614B1
公开(公告)日：2003-01-14
申请号：US09421782
申请日：1999-10-19
申请人： Wei-Jen Li
发明人： Wei-Jen Li
IPC分类号： H04N712
CPC分类号： H04N19/436 , H04N19/42 , H04N19/60 , H04N19/61
摘要： An efficient digital video (DV) decoder process that utilizes a specially constructed quantization matrix allowing an inverse quantization subprocess to perform parallel computations, e.g., using SIMD processing, to efficiently produce a matrix of DCT coefficients. The present invention utilizes a first look-up table (for 8×8 DCT) which produces a 15-valued quantization scale based on class number information and a QNO number for an 8×8 data block (“data matrix”) from an input encoded digital bit stream to be decoded. The 8×8 data block is produced from a deframing and variable length decoding subprocess. An individual 8-valued segment of the 15-value output array is multiplied by an individual 8-valued segment, e.g., “a row,” of the 8×8 data matrix to produce an individual row of the 8×8 matrix of DCT coefficients (“DCT matrix”). The above eight multiplications can be performed in parallel using a SIMD architecture to simultaneously generate a row of eight DCT coefficients. In this way, eight passes through the 8×8 block are used to produce the entire 8×8 DCT matrix, in one embodiment consuming only 33 instructions per 8×8 block. After each pass, the 15-valued output array is shifted by one value position for proper alignment with its associated row of the data matrix. The DCT matrix is then processed by an inverse discrete cosine transform subprocess that generates decoded display data. A second lookup table can be used for 2×4×8 DCT processing.
摘要翻译：一种高效的数字视频（DV）解码器过程，其利用特殊构造的量化矩阵，允许逆量化子过程执行并行计算，例如使用SIMD处理来有效地产生DCT系数矩阵。本发明利用第一查询表（用于8×8CTD），其根据类号信息产生15值量化尺度，并且从输入编码数字比特流（8）的8×8数据块（“数据矩阵”）产生QNO号码被解码。 8x8数据块由解帧和可变长度解码子过程产生。将15值输出阵列的单个8值段乘以8×8数据矩阵的单个8值段，例如“a行”，以产生DCT系数的8×8矩阵的单独行（“DCT” 矩阵”）。可以使用SIMD架构并行地执行上述八个乘法，以同时生成八个DCT系数的行。以这种方式，通过8×8块的八次通过来产生整个8×8的DCT矩阵，在一个实施例中，每8×8块仅消耗33个指令。在每次通过后，15值输出阵列移位一个值位置，以便与其相关联的数据矩阵行正确对齐。 DCT矩阵然后由产生解码显示数据的反离散余弦变换子过程进行处理。第二个查找表可用于2x4x8 DCT处理。

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