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1. 发明申请

US20050050296A1 Method for page sharing in a processor with multiple threads and pre-validated caches 有权
标题翻译：具有多线程和预先验证的缓存的处理器中页面共享的方法
公开(公告)号：US20050050296A1
公开(公告)日：2005-03-03
申请号：US10650335
申请日：2003-08-28
申请人： Sailesh Kottapalli , Nadeem Firasta
发明人： Sailesh Kottapalli , Nadeem Firasta
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1054 , G06F12/1036
摘要： A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.
摘要翻译：公开了一种允许多线程处理器使用翻译后备缓冲器在预先验证的高速缓存中的不同线程上共享页面的方法和系统。多线程处理器搜索翻译后备缓冲区以尝试匹配虚拟内存地址。如果没有找到匹配的有效虚拟内存地址，则检索新的翻译，并搜索匹配的物理内存地址的翻译后备缓冲区。如果找到匹配的物理内存地址，则使用新的翻译覆盖旧的翻译。多线程处理器可以执行切换事件多线程或同时多线程。如果同时执行多线程，则每个线程的访问权限与翻译相关联。

2. 发明申请

US20130311821A1 VIRTUAL DEVICE SPARING 有权
标题翻译：虚拟设备发布
公开(公告)号：US20130311821A1
公开(公告)日：2013-11-21
申请号：US13996717
申请日：2012-03-30
申请人： Brian S. Morris , Sailesh Kottapalli
发明人： Brian S. Morris , Sailesh Kottapalli
IPC分类号： G06F11/20
CPC分类号： G06F11/2094 , G06F11/1658 , G06F11/1666 , G06F11/20 , G06F2201/815
摘要： Systems and techniques for virtual device sharing. A failure of one of a plurality of memory devices corresponding to a first rank in a memory system is detected. The memory system has a plurality of ranks, each rank having a plurality of memory devices used to store a cache line. A portion of the cache line corresponding to the failed memory device is stored in a memory device in a second rank in the memory system and the remaining portion of the cache line in the first rank of the memory system.
摘要翻译：用于虚拟设备共享的系统和技术。检测到与存储器系统中的第一等级对应的多个存储器件中的一个的故障。存储器系统具有多个等级，每个等级具有用于存储高速缓存行的多个存储器件。对应于故障存储器件的高速缓存线的一部分被存储在存储器系统中的第二等级的存储器件中，并且存储器系统的第一级中的高速缓存行的剩余部分被存储。

3. 发明申请

US20130007046A1 DYNAMICALLY ROUTING DATA RESPONSES DIRECTLY TO REQUESTING PROCESSOR CORE 有权
标题翻译：动态路由数据的响应直接要求处理器核心
公开(公告)号：US20130007046A1
公开(公告)日：2013-01-03
申请号：US13175772
申请日：2011-07-01
申请人： Allen J. Baum , Sailesh Kottapalli , Vedaraman Geetha
发明人： Allen J. Baum , Sailesh Kottapalli , Vedaraman Geetha
IPC分类号： G06F17/30
CPC分类号： G06F13/4022
摘要： Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.
摘要翻译：描述了将数据响应直接动态地路由到请求处理器核心的方法和装置。在一个实施例中，响应于数据请求返回的数据将基于存储在路由表中的信息直接发送到请求代理。还公开了其他实施例。

4. 发明申请

US20110252203A1 TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT 有权
公开(公告)号：US20110252203A1
公开(公告)日：2011-10-13
申请号：US13168171
申请日：2011-06-24
申请人： Sailesh Kottapalli , John H. Crawford , Kushagra Vaid
发明人： Sailesh Kottapalli , John H. Crawford , Kushagra Vaid
IPC分类号： G06F12/08
CPC分类号： G06F9/528 , G06F9/3834 , G06F9/544
摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

5. 发明申请

US20110173634A1 Synchronizing Multiple Threads Efficiently 有权
标题翻译：高效同步多线程
公开(公告)号：US20110173634A1
公开(公告)日：2011-07-14
申请号：US13069684
申请日：2011-03-23
申请人： Sailesh Kottapalli , John H. Crawford
发明人： Sailesh Kottapalli , John H. Crawford
IPC分类号： G06F9/46
CPC分类号： G06F9/522 , G06F9/52 , G06F12/084 , G06F12/0842 , G06F12/0857
摘要： In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。以这种方式，当所有线程都到达障碍物时，建立同步。在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。描述和要求保护其他实施例。

6. 发明授权

US07500240B2 Apparatus and method for scheduling threads in multi-threading processors 有权
标题翻译：用于在多线程处理器中调度线程的装置和方法
公开(公告)号：US07500240B2
公开(公告)日：2009-03-03
申请号：US10047809
申请日：2002-01-15
申请人： Ken Shoemaker , Sailesh Kottapalli , Kin-Kee Sit
发明人： Ken Shoemaker , Sailesh Kottapalli , Kin-Kee Sit
IPC分类号： G06F9/46 , G06F15/00 , G06F9/30
CPC分类号： G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.
摘要翻译：提供多线程处理器。多线程处理器包括接收第一线程的第一指令获取单元和用于接收第二线程的第二指令获取单元。耦合到指令提取单元和执行单元的多线程调度器。多线程调度器确定执行单元的宽度，并且执行单元相应地执行线程。

7. 发明申请

US20080215864A1 Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor 审中-公开
标题翻译：同时多线程处理器中指令指针存储元件配置的方法和装置
公开(公告)号：US20080215864A1
公开(公告)日：2008-09-04
申请号：US11638315
申请日：2006-12-12
申请人： Sailesh Kottapalli
发明人： Sailesh Kottapalli
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F9/3867
摘要： A simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again.
摘要翻译：公开了一种同时多线程处理器，其减少了所需的硬件组件的数量以及当前系统上的设计的复杂性。与在处理器流水线内为每个重新转向逻辑组件需要单独的存储元件来保存指令指针信息相反，本发明允许将一个非活动线程的指令指针信息存储在一个“非线程线程”存储元件中，直到线程再次变为活动状态。

8. 发明申请

US20050066151A1 Method and apparatus for handling predicated instructions in an out-of-order processor 审中-公开
标题翻译：用于处理乱序处理器中的预测指令的方法和装置
公开(公告)号：US20050066151A1
公开(公告)日：2005-03-24
申请号：US10666343
申请日：2003-09-19
申请人： Sailesh Kottapalli
发明人： Sailesh Kottapalli
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3017 , G06F9/30072 , G06F9/384
摘要： A method and apparatus for permitting out-of-order execution of predicated instructions is disclosed. In one embodiment, a predicated instruction may be decoded into a related predicated instruction and a move instruction contingent on the complementary value of the predicate of the predicated instruction. The destination register of both the related predicated instruction and the move instruction may be mapped to the same physical register, and only one of the two instructions may update machine state with its results.
摘要翻译：公开了一种用于允许无序执行预定指令的方法和装置。在一个实施例中，预测指令可以被解码成相关的预测指令和移动指令，这取决于预测指令的谓词的互补值。相关的预测指令和移动指令的目标寄存器可以被映射到相同的物理寄存器，并且两个指令中的仅一个可以用其结果来更新机器状态。

9. 发明授权

US10387151B2 Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks 有权
公开(公告)号：US10387151B2
公开(公告)日：2019-08-20
申请号：US13250223
申请日：2011-09-30
申请人： Jonathan C. Hall , Sailesh Kottapalli , Andrew T. Forsyth
发明人： Jonathan C. Hall , Sailesh Kottapalli , Andrew T. Forsyth
IPC分类号： G06F9/312 , G06F9/30 , G06F12/06 , G06F12/08 , G06F9/345
摘要： Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

10. 发明授权

US07984248B2 Transaction based shared data operations in a multiprocessor environment 有权
标题翻译：多处理器环境中基于事务的共享数据操作
公开(公告)号：US07984248B2
公开(公告)日：2011-07-19
申请号：US11027623
申请日：2004-12-29
申请人： Sailesh Kottapalli , John H. Crawford , Kushagra Vaid
发明人： Sailesh Kottapalli , John H. Crawford , Kushagra Vaid
IPC分类号： G06F12/00
CPC分类号： G06F9/528 , G06F9/3834 , G06F9/544
摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.
摘要翻译：本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。在软件中划分的事务被推测执行。在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。如果遇到无效访问，则重新执行该事务。在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。

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