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1. 发明授权

US5742783A System for grouping instructions for multiple issue using plural decoders having forward and backward propagation of decoding information 失效
标题翻译：用于使用具有解码信息的前向和后向传播的多个解码器分组用于多个问题的指令的系统
公开(公告)号：US5742783A
公开(公告)日：1998-04-21
申请号：US293574
申请日：1994-08-22
申请人： Saeid Azmoodeh , Peter Malcolm Keith Boffey , Richard Matthew Forsyth , Brian Jeremy Parsons
发明人： Saeid Azmoodeh , Peter Malcolm Keith Boffey , Richard Matthew Forsyth , Brian Jeremy Parsons
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/3824 , G06F9/3853 , G06F9/3885
摘要： Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.
摘要翻译：计算机设备包括具有多个功能单元（14,16）的指令执行单元（13），每个功能单元（14,16）被布置成执行指令和指令发布电路（10,12）的至少一部分，用于同时发出一组单独的兼容指令所述执行单元（13）具有根据所述执行所述指令所需的每个功能单元对每个指令进行分类的装置，以及用于测试连续指令的分类和根据其分类选择的组的装置兼容于执行单元（13）的同时发布，而对执行单元中的任何功能单元（14,16）没有冲突的要求。

2. 发明授权

US5834860A Controlled impedance transistor switch circuit 失效
标题翻译：受控阻抗晶体管开关电路
公开(公告)号：US5834860A
公开(公告)日：1998-11-10
申请号：US431482
申请日：1995-05-01
申请人： Brian Jeremy Parsons , Robert John Simpson
发明人： Brian Jeremy Parsons , Robert John Simpson
IPC分类号： H03K17/66 , G11C7/10 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03K17/167 , G11C7/1051 , H03K17/164
摘要： An output driver circuit comprises a plurality of parallel pull up and pull down circuits each comprising at least one transistor switch switchable between on and off states and circuitry operable to maintain a desired resistance in the circuit when the transistor switch is switched on, and switch actuating circuitry including time delay circuitry for effecting a sequence of transistor switching operations in said pull-up and pull-down circuits with a time delay between successive operations, each operation effecting simultaneous switching of a transistor in one pull-up circuit and one pull-down circuit, whereby the output impedance is stabilised during a change in signal on the output terminal.
摘要翻译：输出驱动器电路包括多个并行上拉和下拉电路，每个并联上拉和下拉电路包括可在导通和截止状态之间切换的至少一个晶体管开关和可操作以在晶体管开关导通时保持电路中所需电阻的电路，以及开关致动电路包括用于在连续操作之间以时间延迟来实现所述上拉和下拉电路中的一系列晶体管开关操作的时间延迟电路，每个操作实现一个上拉电路中的晶体管的同时切换和一个下拉电路，由此在输出端子上的信号变化期间输出阻抗稳定。

3. 发明授权

US3983537A Reliability of random access memory systems 失效
标题翻译：随机存取存储器系统的可靠性
公开(公告)号：US3983537A
公开(公告)日：1976-09-28
申请号：US456647
申请日：1974-04-01
申请人： Brian Jeremy Parsons , Lynne Margaret Pursell
发明人： Brian Jeremy Parsons , Lynne Margaret Pursell
IPC分类号： G06F11/00 , G06F12/06 , G06F12/08 , G11C29/00 , G11C11/00
CPC分类号： G11C29/785 , G06F11/006 , G06F12/0661 , G06F12/08 , G11C29/808
摘要： A digital memory is configured as a hierarchical system with at least three levels. The first level consists of a main bus and interfacing for one or more main memory units; the second level consists of a separate second level bus in each main memory unit with a plurality of memory frames independently interfaced to each bus; and the third level consists of a separate third level bus in each memory frame with a plurality of memory storage blocks independently interfaced to each bus. Virtual addressing is employed in which the whole of each address is decoded in the individual memory block which includes for the purpose soft-ware settable registers containing identification numbers.
摘要翻译：数字存储器被配置为具有至少三个级别的分级系统。第一级包括主总线和一个或多个主存储器单元的接口; 第二级由每个主存储器单元中的单独的第二级总线组成，其中多个存储器帧独立地连接到每个总线; 并且第三级由每个存储器帧中的单独的第三级总线组成，其具有独立地与每个总线接口的多个存储器存储块。采用虚拟寻址，其中每个地址的整体在各个存储块中被解码，该存储块包括用于包含标识号的软件可设置寄存器。

4. 发明授权

US3932734A Binary parallel adder employing high speed gating circuitry 失效
标题翻译：采用高速选通电路的二进制并行加法器
公开(公告)号：US3932734A
公开(公告)日：1976-01-13
申请号：US449461
申请日：1974-03-08
申请人： Brian Jeremy Parsons
发明人： Brian Jeremy Parsons
IPC分类号： G06F7/50 , G06F7/503
CPC分类号： G06F7/503
摘要： In a binary parallel complementing L.S.I. adder, a C-MOS transmission gate is provided in each stage with its input and output directly connected to the carry in and carry out leads of the stage. The gate is switched by complementary control bits derived by stage input logic operating on the bits to be summed, whereby very fast passage of a carry through the stages is achieved. The transmission gate consists of p- and n- channel MOS transistors with their sources connected in common to the input and their drain electrodes likewise connected in common to the output.
摘要翻译：在二进制并行互补L.S.I. 加法器，在每个级中提供C-MOS传输门，其输入和输出直接连接到进位并执行级的引线。栅极由通过对要相加的位进行工作的级输入逻辑导出的互补控制位进行切换，从而实现进位通过级的非常快速的通过。传输门由p沟道MOS晶体管和n沟道MOS晶体管组成，其源极与输入端共同连接，漏极电极同样连接到输出端。

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