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1. 发明申请

WO2013191873A2 GENERATION OF MEMORY STRUCTURAL MODEL BASED ON MEMORY LAYOUT 审中-公开
标题翻译：基于存储器布局的存储器结构模型的生成
公开(公告)号：WO2013191873A2
公开(公告)日：2013-12-27
申请号：PCT/US2013/043767
申请日：2013-05-31
申请人： SYNOPSYS, INC.
发明人： AMIRKHANYAN, Karen , DARBINYAN, Karen , DAVTYAN, Arman , HARUTYUNYAN, Gurgen , SHOUKOURIAN, Samvel , VARDANIAN, Valery , ZORIAN, Yervant
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5081 , G06F2217/02 , G06F2217/14
摘要： A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.
摘要翻译：存储器结构模型以有效的方式直接从存储器配置信息和存储器布局信息生成。通过分析存储器的配置信息和相应的存储器布局来生成带分布的信息。通过使用物理位模式对存储器布局进行编程，提取对应的逻辑位模式，然后分析物理位模式与逻辑位模式之间的差异来产生关于存储器布局中地址加扰的信息。带分布信息和地址扰乱信息被组合到用于设计有效的测试和修复引擎的存储器结构模型中。

2. 发明申请

WO2013043615A1 MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES 审中-公开
标题翻译：用于测试嵌入式存储器的内存硬分区优化
公开(公告)号：WO2013043615A1
公开(公告)日：2013-03-28
申请号：PCT/US2012/055944
申请日：2012-09-18
申请人： SYNOPSYS, INC.
发明人： ZORIAN, Yervant , DARBINYAN, Karen , TORJYAN, Gevorg
IPC分类号： G01R31/28
CPC分类号： G06F17/5031 , G01R31/318536 , G01R31/318572 , G06F17/505 , G06F17/5068 , G11C29/12 , G11C29/16 , G11C29/32 , G11C2029/0401
摘要： A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.
摘要翻译：设计用于支持具有与DFT技术相关联的信号路径和共享逻辑设备或组件的存储器实例的功能操作的测试（DFT）技术的多个设计的存储器硬宏。存储器硬宏包括功能输入端口和功能输出端口，形成功能存储器数据路径，其包括来自存储器实例的输入锁存器。存储器硬宏还包括扫描输入端口和扫描输出端口，形成扫描数据路径，其包括来自数据缓冲电路阵列的输入锁存器和来自读出放大器阵列的输出锁存器。存储器硬宏还包括BIST输入端口和BIST输出端口，形成BIST数据路径，其包括来自数据缓冲器电路阵列的至少一个输入锁存器和来自读出放大器阵列的至少一个输出锁存器。

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