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    • 3. 发明申请
    • METHODS FOR OPERATING A CPU HAVING AN INTERNAL DATA CACHE
    • 用于操作内部数据缓存的CPU的方法
    • WO2004023312A1
    • 2004-03-18
    • PCT/SG2002/000176
    • 2002-08-05
    • INFINEON TECHNOLGIES AGKAMIKO, TaroPANDEY, Pramod
    • KAMIKO, TaroPANDEY, Pramod
    • G06F12/08
    • G06F12/0638G06F12/0802
    • A CPU 3 having a processor 1 and an internal data cache 7 IS operated in combination with a dummy interface 13 which simulates the existence of an external memory 17 having the same address space as the cache memory 7 but which does not store data written to it. In this way, a conventional CPU can be operated without read/write access to an external memory in respect of at least part of its memory address space, and therefore with a higher performance resulting from faster memory access and reduced external memory requirements. The CPU 3 may be one of a set of CPU chips 20, 21 in a data processing system, one or more of those chips 20 optionally having read/write access to an external memory 23.
    • 具有处理器1和内部数据高速缓冲存储器7的CPU 3与虚拟接口13组合操作,该虚拟接口模拟存在与高速缓冲存储器7相同的地址空间的外部存储器17,但不存储写入其中的数据 。 以这种方式,传统的CPU可以相对于其存储器地址空间的至少一部分而无需对外部存储器的读/写访问,因此具有由于更快的存储器访问和减少的外部存储器要求而导致的更高的性能。 CPU 3可以是数据处理系统中的一组CPU芯片20,21中的一个,这些芯片20中的一个或多个可选地具有对外部存储器23的读/写访问。