专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0881669B1 Manufacturing process of a germanium implanted heterojunction bipolar transistor 失效
标题翻译：一种用于生产锗注入双极异质结晶体管的过程
公开(公告)号：EP0881669B1
公开(公告)日：2005-12-14
申请号：EP97830259.4
申请日：1997-05-30
申请人： STMicroelectronics S.r.l. , CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Lombardo, Salvatore , Pinto, Angelo , Nicotra, Maria Concetta
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/26506

2. 发明公开

EP0881669A1 Manufacturing process of a germanium implanted HBT bipolar transistor 失效
标题翻译： Verfahren zur Herstellung eines Germanium-implantierten bipolarenHeteroübergang晶体管
公开(公告)号：EP0881669A1
公开(公告)日：1998-12-02
申请号：EP97830259.4
申请日：1997-05-30
申请人： STMicroelectronics S.r.l. , CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
发明人： Lombardo, Salvatore , Pinto, Angelo , Nicotra, Maria Concetta
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/26506
摘要： A process for fabricating a vertical structure high carrier mobility transistor on a substrate (1) of crystalline silicon doped with impurities of the N type, having a collector region (2) located at a lower portion of the substrate, the process comprising the steps of:

defining a window (10) in the semiconductor substrate (1);
providing a first implantation of germanium (Ge) atoms through said window (10);
providing a second implantation of acceptor dopants through said window (10) to define a base region;
applying an RTA treatment, or treatment in an oven, to reconstruct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy (Si 1-x Ge x );
forming a first thin dielectric layer (12) of silicon dioxide (SiO 2 ) by chemical vapor deposition; depositing a second dielectric layer (14) onto said first dielectric layer (12);
depositing a polysilicon layer (15) onto said second dielectric layer (14);
etching away, within the window region (10), said first (12) and second (14) dielectric layers, and the polysilicon layer (15), to expose the base region (3) and form isolation spacers (50) at the window edges;
forming an N-doped emitter (4) in the base (3) and window regions.

This fabrication process is specially attentive to the formation of the silicon dioxide SiO 2 /Ge x Si 1-x interface present in vertical structure HBT transistors, if isolation spacers are to be formed.
The fabrication process of this invention allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base currents from the ideal.
摘要翻译：一种用于在掺杂有N型杂质的晶体硅的衬底（1）上制造垂直结构的高载流子迁移率晶体管的方法，其具有位于衬底下部的集电极区域（2），该方法包括以下步骤：：在所述半导体衬底（1）中限定窗口（10）; 提供通过所述窗口（10）的锗（Ge）原子的第一注入; 提供通过所述窗口（10）的受体掺杂剂的第二注入以限定基极区域; 在烘箱中进行RTA处理或处理以重构包括硅/锗合金（Si1-xGex）的半导体衬底内的晶格; 通过化学气相沉积形成二氧化硅（SiO 2）的第一薄介电层（12）; 将第二介电层（14）沉积到所述第一介电层（12）上; 将多晶硅层（15）沉积到所述第二介电层（14）上; 在窗口区域（10），所述第一（12）和第二（14）电介质层和多晶硅层（15）之间蚀刻掉，以暴露基部区域（3）并在窗口处形成隔离间隔物（50）边缘; 在基底（3）和窗口区域中形成N掺杂发射体（4）。如果要形成隔离间隔物，则该制造工艺特别注意垂直结构HBT晶体管中存在的二氧化硅SiO 2 / G x Si 1-x界面的形成。本发明的制造方法允许HBT晶体管的应用频率域进一步扩展，同时消除基极电流与理想电流的偏差。

3. 发明公开

EP1005091A1 A method of manufacturing a vertical-channel MOSFET 有权
标题翻译： Methode zur Herstellung von einem MOSFET mit einem vertikalen Kanal
公开(公告)号：EP1005091A1
公开(公告)日：2000-05-31
申请号：EP98830690.8
申请日：1998-11-17
申请人： STMicroelectronics S.r.l.
发明人： Patti, Davide , Pinto, Angelo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/76221 , H01L21/763 , H01L21/8249 , H01L29/7827
摘要： The following steps are performed on a wafer of semiconductor material having a layer (1) with n conductivity: a) implanting n impurity ions and p impurity ions in an area of the layer and subjecting the wafer to a high-temperature treatment; the impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first, p region (49) and a second, n region (50) which forms a pn junction with the first region (49); b) hollowing out a trench (43) which intersects the first region (49) and the second region (50), c) forming a dielectric coating (44) on the lateral surface of the trench (43), d) depositing electrically-conductive material (51) in the trench (43) in contact with the dielectric (44), and e) forming elements (60, 61, 62) for electrical contact with the layer (1), with the second region (50), and with the electrically-conductive material (51) inside the trench (43), in order to produce drain (D), source (S) and gate (G) electrodes of the MOSFET, respectively. A submicrometric vertical-channel MOSFET of optimal quality and reproducibility is thus produced by a method compatible with DPSA technology.
摘要翻译：在具有n导电性的层（1）的半导体材料的晶片上进行以下步骤：a）在层的区域中注入n个杂质离子和p杂质离子，并对晶片进行高温处理; 杂质，注入剂量和能量，以及高温处理时间和温度，以形成与第一区域形成pn结的第一p区（49）和第二n区（50） 49）; b）挖空与第一区域（49）和第二区域（50）相交的沟槽（43），c）在沟槽（43）的侧表面上形成电介质涂层（44），d）与所述电介质（44）接触的所述沟槽（43）中的导电材料（51），以及e）与所述第二区域（50）形成用于与所述层（1）电接触的元件（60,61,62）并且沟槽（43）内部的导电材料（51）分别产生MOSFET的漏极（D），源极（S）和栅极（G）电极。因此，通过与DPSA技术兼容的方法产生了具有最佳质量和重现性的亚微米级垂直沟道MOSFET。

4. 发明公开

EP0881688A1 PNP lateral bipolar electronic device 失效
标题翻译： om ches v v v v。。。。。。。。。。。
公开(公告)号：EP0881688A1
公开(公告)日：1998-12-02
申请号：EP97830257.8
申请日：1997-05-30
申请人： STMicroelectronics S.r.l.
发明人： Pinto, Angelo , Alemanni, Carlo
IPC分类号： H01L29/735 , H01L29/417 , H01L27/082
CPC分类号： H01L29/41708 , H01L27/0823 , H01L29/735
摘要： A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises:

the semiconductor substrate (10), doped for conductivity of the P type;
a first buried layer (12), doped for conductivity of the N type to provide a base region;
a second layer (13), overlying the first and having conductivity of the N type, to provide an active area distinguishable by a P-doped emitter region (14) within the active area being located peripherally and oppositely from a P-doped collector region (15).

The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.
摘要翻译：横向PNP双极电子器件与半导体衬底上的整体集成，以及能够在高频下工作的其他NPN双极器件。 PNP器件被结合到电绝缘的多层结构中，其包括：掺杂为P型导电性的半导体衬底（10）; 掺杂为N型导电性以提供基极区域的第一掩埋层（12）; 覆盖第一层并具有N型导电性的第二层（13），以提供由有源区域内的P掺杂发射极区域（14）可区分的有源区域，其位于P掺杂收集极区域周围和相对的位置（15）。横向PNP器件可以以合适的集电极电流值和良好的放大率在高频下工作，与典型的常规横向PNP器件相比，可提供优异的品质因数。

5. 发明授权

EP0881689B1 PNP lateral bipolar electronic device and corresponding manufacturing process 失效
标题翻译：横向PNP双极电子元件及其制造方法
公开(公告)号：EP0881689B1
公开(公告)日：2002-08-07
申请号：EP97830260.2
申请日：1997-05-30
申请人： STMicroelectronics S.r.l.
发明人： Pinto, Angelo , Alemanni, Carlo
IPC分类号： H01L29/735 , H01L21/331 , H01L27/082 , H01L21/8228
CPC分类号： H01L29/6625 , H01L21/8228 , H01L27/082 , H01L29/735

6. 发明授权

EP1005091B1 A method of manufacturing a vertical-channel MOSFET 有权
标题翻译：用于制造MOSFET的具有垂直信道的方法
公开(公告)号：EP1005091B1
公开(公告)日：2002-07-10
申请号：EP98830690.8
申请日：1998-11-17
申请人： STMicroelectronics S.r.l.
发明人： Patti, Davide , Pinto, Angelo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/76221 , H01L21/763 , H01L21/8249 , H01L29/7827

7. 发明公开

EP0881689A1 PNP lateral bipolar electronic device and corresponding manufacturing process 失效
标题翻译： Laterales PNP-bipolares elektronisches Bauelement und dessen Herstellungsverfahren
公开(公告)号：EP0881689A1
公开(公告)日：1998-12-02
申请号：EP97830260.2
申请日：1997-05-30
申请人： STMicroelectronics S.r.l.
发明人： Pinto, Angelo , Alemanni, Carlo
IPC分类号： H01L29/735 , H01L21/331
CPC分类号： H01L29/6625 , H01L21/8228 , H01L27/082 , H01L29/735
摘要： The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure and comprising:

the semiconductor substrate, doped with impurities of the P type;
a first buried layer, doped with impurities of the N type to form a base region;
a second layer (13), overlying the first and having conductivity of the N type, to form an active area; opposite collector (12) and emitter (14) regions being formed in said active area and separated by a base channel region; characterized in that the width of the base channel is defined essentially by a contact opening (18) formed above an oxide layer (11) protecting the base channel. Advantageously, the opening (18) is formed by shifting an emitter mask.
摘要翻译：本发明涉及一种用于制造横向PNP双极电子器件的方法，其与NPN型的其它双极器件一体地集成在半导体衬底上，所述器件被并入到电绝缘的多层结构中，并且包括：掺杂有杂质的半导体衬底的P型; 第一掩埋层，掺杂有N型杂质以形成基极区; 覆盖第一层并具有N型导电性的第二层（13）以形成有源区; 相反的集电极（12）和发射极（14）区域形成在所述有源区域中并由基极沟道区域分隔开; 其特征在于，基部通道的宽度基本上由形成在保护基底通道的氧化物层（11）上方的接触开口（18）限定。有利地，通过移动发射器掩模来形成开口（18）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式