专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2004042602A1 APPARATUS TO IMPLEMENT DUAL HASH ALGORITHM 审中-公开
标题翻译：实现双重哈希算法的设备
公开(公告)号：WO2004042602A1
公开(公告)日：2004-05-21
申请号：PCT/SG2002/000245
申请日：2002-10-21
申请人： STMICROELECTRONICS ASIA PACIFIC PTE LTD. , PLESSIER, Bernard , MING, Kiat. Yap
发明人： PLESSIER, Bernard , MING, Kiat. Yap
IPC分类号： G06F17/10
CPC分类号： H04L9/0643 , H04L2209/04 , H04L2209/12
摘要： Apparatus is disclosed which is arranged to accept digital data as an input, and to process said data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word. The apparatus includes a pluraity of rotational registers for storing data, one of the registers being arranged to receive the input data, and data stores for initialisation of some of said plurality of registers according to whether the SHA-1 or MD5 algorithm is used. The data stores include fixed data relating to SHA-1 and MD5 operation. Also included is a plurality of dedicated combinatorial logic circuits arranged to perform logic operations on data stored in selected ones of said plurality of registers.
摘要翻译：公开了被设置为接受数字数据作为输入并且根据安全散列算法（SHA-1）或消息摘要（MD5）算法之一处理所述数据以产生固定长度输出字的装置。该装置包括用于存储数据的旋转寄存器，根据是否使用SHA-1或MD5算法，寄存器中的一个被布置为接收输入数据，以及用于初始化所述多个寄存器中的一些的数据存储。数据存储包括与SHA-1和MD5操作有关的固定数据。还包括多个专用组合逻辑电路，其被布置为对存储在所述多个寄存器中的选定寄存器中的数据执行逻辑运算。

2. 发明公开

EP1556781A1 APPARATUS TO IMPLEMENT DUAL HASH ALGORITHM 审中-公开
标题翻译： DEVICE FOR携带两个散列算法
公开(公告)号：EP1556781A1
公开(公告)日：2005-07-27
申请号：EP02778181.4
申请日：2002-10-21
申请人： STMicroelectronics Asia Pacific Pte Ltd.
发明人： PLESSIER, Bernard , MING, Kiat. Yap
IPC分类号： G06F17/10
CPC分类号： H04L9/0643 , H04L2209/04 , H04L2209/12
摘要： Apparatus is disclosed which is arranged to accept digital data as an input, and to process said data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word. The apparatus includes a pluraity of rotational registers for storing data, one of the registers being arranged to receive the input data, and data stores for initialisation of some of said plurality of registers according to whether the SHA-1 or MD5 algorithm is used. The data stores include fixed data relating to SHA-1 and MD5 operation. Also included is a plurality of dedicated combinatorial logic circuits arranged to perform logic operations on data stored in selected ones of said plurality of registers.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式