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1. 发明申请

WO2006121489A2 COMPACT MODULE SYSTEM AND METHOD 审中-公开
标题翻译：紧凑型模块系统和方法
公开(公告)号：WO2006121489A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/007193
申请日：2006-02-28
申请人： STAKTEK GROUP L.P. , CADY, James, W. , WEHRLY, James, Douglas, Jr. , GOODWIN, Paul
发明人： CADY, James, W. , WEHRLY, James, Douglas, Jr. , GOODWIN, Paul
IPC分类号： G06F11/00
CPC分类号： H05K1/189 , H05K2201/056 , H05K2201/10159 , H05K2201/10189
摘要： A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form that provides structure to create a module with plural layers of circuitry in a single module. In preferred embodiments, the form is metallic and, in alternative preferred embodiments, the module circuitry is disposed within a housing. Preferred embodiments may be devised that present a compact flash module within a housing that may be connected to or into a system or product through a connective facility that is preferably a male or female socket connector while the housing is configured to mechanically adapt to an application environment.
摘要翻译：柔性电路填充在一侧或两侧并且设置在基板周围以形成电路模块。沿着其边缘之一，柔性电路连接到诸如多针连接器的连接设备，而柔性电路围绕导热形式设置，其提供结构以在单个模块中创建具有多层电路的模块。在优选实施例中，该形式是金属的，并且在替代优选实施例中，模块电路设置在壳体内。可以设计出优选实施例，其在壳体内呈现紧凑型闪光模块，其可以通过连接设备连接到系统或产品，该连接设备优选地是公插座或母插座连接器，而壳体被配置成机械地适应应用环境。

2. 发明申请

WO2004109802A1 MEMORY EXPANSION AND INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD 审中-公开
标题翻译：内存扩展和集成电路堆叠系统和方法
公开(公告)号：WO2004109802A1
公开(公告)日：2004-12-16
申请号：PCT/US2003/029000
申请日：2003-09-15
申请人： STAKTEK GROUP, L.P. , RAPPORT, Russell , CADY, James, W. , WILDER, James , ROPER, David, L. , WEHRLY, James, Douglas, Jr. , BUCHLE, Jeff
发明人： RAPPORT, Russell , CADY, James, W. , WILDER, James , ROPER, David, L. , WEHRLY, James, Douglas, Jr. , BUCHLE, Jeff
IPC分类号： H01L25/10
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

3. 发明申请

WO2007001505A3 DIE MODULE SYSTEM AND METHOD 审中-公开
公开(公告)号：WO2007001505A3
公开(公告)日：2007-01-04
申请号：PCT/US2006/006935
申请日：2006-02-27
申请人： STAKTEK GROUP L.P. , CADY, James, W. , GOODWIN, Paul
发明人： CADY, James, W. , GOODWIN, Paul
IPC分类号： H05K1/11 , H01K1/14
摘要： A flex circuit is populated on one or both sides with plural integrated circuit die. In a preferred mode, the flex circuit is populated with flip-chip die. One side of the flex circuit has a connective facility implemented in a preferred mode with edge connector contacts. The flex circuit is disposed about a substrate to form a circuit module that may be inserted into an edge connector such as ones typically found on a computer board.

4. 发明申请

WO2007044368A2 MINIMIZED PROFILE CIRCUIT MODULE SYSTEMS AND METHODS 审中-公开
标题翻译：最小化型式电路模块系统和方法
公开(公告)号：WO2007044368A2
公开(公告)日：2007-04-19
申请号：PCT/US2006/038720
申请日：2006-10-03
申请人： STAKTEK GROUP L.P. , CADY, James, W. , WEHRLY, James, Douglas , GOODWIN, Paul
发明人： CADY, James, W. , WEHRLY, James, Douglas , GOODWIN, Paul
IPC分类号： H01R43/02
CPC分类号： G11C5/143 , G11C5/04 , H01L23/5387 , H01L25/0652 , H01L25/105 , H01L25/50 , H01L2924/0002 , H05K1/0203 , H05K1/118 , H05K1/181 , H05K1/189 , H05K3/0061 , H05K2201/056 , H05K2201/1056 , H05K2201/10734 , H05K2201/2018 , H05K2203/1572 , Y10T29/4913 , Y10T29/49179 , H01L2924/00
摘要： Flexible circuitry is populated on one or both sides with integrated circuits (ICs) each of which ICs has an IC profile (height). A substantially flat, windowed fixture with a fixture profile less than the IC profiles of the ICs is applied over an IC-populated side of the flexible circuitry causing at least a part of the ICs to emerge from respective fixture windows. Material is removed simultaneously from that portion of the ICs that emerge from the windows to result in lower-profile ICs which, in a preferred embodiment exhibit profiles substantially coincident with the fixture profile established by the upper surface of the fixture. The method is used to advantage in devising circuit modules by disposing the flexible circuitry about a rigid substrate to form the circuit module with a low profile. Some embodiments use substrates that are windowed or have inset areas into which the lower profile CSPs may be set to reach profile requirements.
摘要翻译：灵活的电路在一侧或两侧安装集成电路（IC），每个IC都具有IC配置文件（高度）。具有小于IC的IC配置文件的夹具型材的基本平坦的窗口固定件被施加在柔性电路的IC填充侧上，导致至少一部分IC从相应的固定窗口露出。与从窗户出现的IC的那部分同时移除材料以产生下轮廓的IC，其在优选实施例中表现出与由固定装置的上表面确定的夹具轮廓基本一致的轮廓。该方法用于通过将柔性电路围绕刚性基板布置以形成具有低轮廓的电路模块来设计电路模块。一些实施例使用被窗口化或具有插入区域的衬底，下部轮廓CSP可被设置到其中以达到轮廓要求。

5. 发明申请

WO2003037053A1 CHIP SCALE STACKING SYSTEM AND METHOD 审中-公开
标题翻译：芯片尺寸堆叠系统和方法
公开(公告)号：WO2003037053A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/034340
申请日：2002-10-25
申请人： STAKTEK GROUP, L.P. , CADY, James, W. , WILDER, James , ROPER, David, L. , WEHRLY, James, Douglas , DOWDEN, Julian , BUCHLE, Jeff
发明人： CADY, James, W. , WILDER, James , ROPER, David, L. , WEHRLY, James, Douglas , DOWDEN, Julian , BUCHLE, Jeff
IPC分类号： H05K7/06
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01087 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module (10) devised in accordance with a preferred embodiment of the present invention, a pair of CSPs (12, 14) is stacked, with one CSP (12) above the other (14). The two CSPs are connected with a pair of flexible circuit structures (30, 32). Each of the pair of flexible circuit structures (30, 32) is partially wrapped about a respective opposite lateral edge (20, 22) of the lower CSP (14) of the module (10). The flex circuit pair (30, 32) connects the upper and lower CSPs (12, 14) and provides a thermal and electrical path connection path between the module (10) and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成节省板表面积的模块。在根据本发明的优选实施例设计的两高CSP堆栈或模块（10）中，堆叠一对CSP（12,14），其中一个CSP（12）在另一个之上（14）。两个CSP与一对柔性电路结构（30,32）连接。一对柔性电路结构（30,32）中的每一个围绕模块（10）的下CSP（14）的相应的相对的侧边缘（20,22）部分地缠绕。柔性电路对（30,32）连接上部和下部CSP（12,14），并且在模块（10）和诸如印刷线路板（PWB）的应用环境之间提供热和电路径连接路径。本发明可以有利于提供用于高密度存储器或高容量计算的模块中的CSP的多种配置和组合。

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