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1. 发明授权

EP0103355B1 Analog to digital converting system for a video signal 失效
标题翻译：模拟到视频信号的数字转换系统
公开(公告)号：EP0103355B1
公开(公告)日：1987-09-16
申请号：EP83303437.4
申请日：1983-06-14
申请人： SONY CORPORATION
发明人： Iwase, Seiichiro , Komori, Shinichi
IPC分类号： H04N9/64
CPC分类号： H04N9/64

2. 发明公开

EP0103355A3 Analog to digital converting system for a video signal 失效
标题翻译：模拟到视频信号的数字转换系统
公开(公告)号：EP0103355A3
公开(公告)日：1984-10-24
申请号：EP83303437
申请日：1983-06-14
申请人： SONY CORPORATION
发明人： Iwase, Seiichiro , Komori, Shinichi
IPC分类号： H04N09/535
CPC分类号： H04N9/64
摘要： An analog to digital converting system for a video signal is disclosed in which an analog video signal is fed to an analog to digital converter, then converted to a digital video signal, a digital burst signal is extracted from the digital video signal thus converted, the digital burst signal is multiplied by first and second AC signals having the same frequency as the burst frequency but different in phase to each other to produce first and second digital product signals, first and second digital signals representing DC components are derived from the first and second digital product signals, and the first and second digital signals are calculated to thereby control the phase of the sampling clock at the analog to digital converter.

3. 发明公开

EP0103355A2 Analog to digital converting system for a video signal 失效
标题翻译：模拟到数字转换系统的视频信号。
公开(公告)号：EP0103355A2
公开(公告)日：1984-03-21
申请号：EP83303437.4
申请日：1983-06-14
申请人： SONY CORPORATION
发明人： Iwase, Seiichiro , Komori, Shinichi
IPC分类号： H04N9/64
CPC分类号： H04N9/64
摘要： An analog to digital converting system for a video signal is disclosed in which an analog video signal is fed to an analog to digital converter, then converted to a digital video signal, a digital burst signal is extracted from the digital video signal thus converted, the digital burst signal is multiplied by first and second AC signals having the same frequency as the burst frequency but different in phase to each other to produce first and second digital product signals, first and second digital signals representing DC components are derived from the first and second digital product signals, and the first and second digital signals are calculated to thereby control the phase of the sampling clock at the analog to digital converter.

4. 发明授权

EP0182602B1 Digital filter 失效
公开(公告)号：EP0182602B1
公开(公告)日：1992-03-11
申请号：EP85308269.1
申请日：1985-11-13
申请人： SONY CORPORATION
发明人： Iwase, Seiichiro , Yamazaki, Takao
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/0202

5. 发明公开

EP0182602A3 Digital filter 失效
标题翻译：数字滤波器
公开(公告)号：EP0182602A3
公开(公告)日：1987-09-02
申请号：EP85308269
申请日：1985-11-13
申请人： SONY CORPORATION
发明人： Iwase, Seiichiro , Yamazaki, Takao
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/0202
摘要： A digital filter comprising, an input terminal provided with an input digital signal, a delay circuit connected to the input terminal and for producing a plurality of delayed digital signals each having different delay time with respect to the input digital signal, a first circuit for selectively adding the input digital signal and/or the plurality of delayed digital signals to be multiplied with one or more digital coefficient signals of same value so as to produce one or more added digital signals, a circuit for multiplying the one or more respective digital coefficient signals to the one or more added digital signals and/or one or more of the plurality of delayed digital signals, respectively a plurality of multiplied digital signals, second circuit for adding the plurality of multiplied digital signals so as to produce an output digital signal, and a circuit connected between the delay circuit and a circuit for multiplying and for increasing the one or more added digital signals and/or the one or more of the plurality of delayed digital signals in the value thereof by one or more predetermined numbers of times, whereby the one or more respective digital coefficient signals have inversely proportional values corresponding to the one or more predetermined numbers of times of the values of the one or more added digital signals and/ or the one or more of the plurality of delayed digital signals.

6. 发明公开

EP0182602A2 Digital filter 失效
标题翻译：数字滤波器。
公开(公告)号：EP0182602A2
公开(公告)日：1986-05-28
申请号：EP85308269.1
申请日：1985-11-13
申请人： SONY CORPORATION
发明人： Iwase, Seiichiro , Yamazaki, Takao
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/0202
摘要： A digital filter comprising, an input terminal provided with an input digital signal, a delay circuit connected to the input terminal and for producing a plurality of delayed digital signals each having different delay time with respect to the input digital signal, a first circuit for selectively adding the input digital signal and/or the plurality of delayed digital signals to be multiplied with one or more digital coefficient signals of same value so as to produce one or more added digital signals, a circuit for multiplying the one or more respective digital coefficient signals to the one or more added digital signals and/or one or more of the plurality of delayed digital signals, respectively a plurality of multiplied digital signals, second circuit for adding the plurality of multiplied digital signals so as to produce an output digital signal, and a circuit connected between the delay circuit and a circuit for multiplying and for increasing the one or more added digital signals and/or the one or more of the plurality of delayed digital signals in the value thereof by one or more predetermined numbers of times, whereby the one or more respective digital coefficient signals have inversely proportional values corresponding to the one or more predetermined numbers of times of the values of the one or more added digital signals and/ or the one or more of the plurality of delayed digital signals.

7. 发明授权

EP0158980B1 Digital time base corrector 失效
标题翻译：数字时基校正器
公开(公告)号：EP0158980B1
公开(公告)日：1992-07-08
申请号：EP85104421.4
申请日：1985-04-11
申请人： SONY CORPORATION
发明人： Shirota, Norihisa , Yamazaki, Takao , Iwase, Seiichiro
IPC分类号： G06F5/06
CPC分类号： H03K5/131 , G11B20/18 , H03K2005/00241 , H04N5/95

8. 发明公开

EP0158980A3 Digital time base corrector 失效
标题翻译：数字时基校正器
公开(公告)号：EP0158980A3
公开(公告)日：1989-09-06
申请号：EP85104421.4
申请日：1985-04-11
申请人： SONY CORPORATION
发明人： Shirota, Norihisa , Yamazaki, Takao , Iwase, Seiichiro
IPC分类号： G06F5/06
CPC分类号： H03K5/131 , G11B20/18 , H03K2005/00241 , H04N5/95
摘要： There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit (11, 51). A signal selecting circuit (12) is divided into N first unit selecting circuits (21, 22, 23, 24) and a second unit selecting circuit (25). M of the output signals of a shift register (R 1 , R 2 , ...) are inputted to the first unit selecting circuits (21, 22, 23, 24), by which one of them is selected. The outputs of the N first unit selecting circuits (21, 22, 23, 24) are supplied to the second unit selecting circuit (25), by which one of them is selected. A pipeline process is performed by inserting a delay circuit (R 21 , R 22 , R 23 , R 2 4) to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit (25). Further, the selecting signal can be made variable for every one clock and a delay circuit (33,37) is inserted on the output side of a selecting signal forming circuit (13). With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

9. 发明公开

EP0158980A2 Digital time base corrector 失效
标题翻译：数字时基校正器
公开(公告)号：EP0158980A2
公开(公告)日：1985-10-23
申请号：EP85104421.4
申请日：1985-04-11
申请人： SONY CORPORATION
发明人： Shirota, Norihisa , Yamazaki, Takao , Iwase, Seiichiro
IPC分类号： G06F5/06
CPC分类号： H03K5/131 , G11B20/18 , H03K2005/00241 , H04N5/95
摘要： There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit (11, 51). A signal selecting circuit (12) is divided into N first unit selecting circuits (21, 22, 23, 24) and a second unit selecting circuit (25). M of the output signals of a shift register (R 1 , R 2 , ...) are inputted to the first unit selecting circuits (21, 22, 23, 24), by which one of them is selected. The outputs of the N first unit selecting circuits (21, 22, 23, 24) are supplied to the second unit selecting circuit (25), by which one of them is selected. A pipeline process is performed by inserting a delay circuit (R 21 , R 22 , R 23 , R 2 4) to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit (25). Further, the selecting signal can be made variable for every one clock and a delay circuit (33,37) is inserted on the output side of a selecting signal forming circuit (13). With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.
摘要翻译：提供了一种数字时基校正器，其中由连续数据时间序列组成的一个数据块的数字输入信号由可变延迟电路（11,51）转换为包括数据缺失间隔的数字信号，反之亦然。信号选择电路（12）被分成N个第一单元选择电路（21,22,23,24）和第二单元选择电路（25）。移位寄存器（R1，R2，...）的输出信号的M被输入到第一单元选择电路（21,22,23,24），通过它们中的一个被选择。 N个第一单元选择电路（21,22,23,24）的输出被提供给第二单元选择电路（25），通过它们中的一个被选择。通过插入延迟电路（R21，R22，R23，R24）以将信号延迟一个时钟周期的时间到第二单元选择电路（25）的输入/输出线中来执行流水线处理。此外，选择信号可以在每个时钟中变化，并且延迟电路（33,37）被插入选择信号形成电路（13）的输出侧。利用该校正器，可以减少选择器的门延迟的影响并且可以执行高速数据处理。

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