专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

DE69633989D1 未知
公开(公告)号：DE69633989D1
公开(公告)日：2005-01-13
申请号：DE69633989
申请日：1996-05-30
申请人： SONY CORP
发明人： SHIRAHAMA AKIRA , TAMURA TAKAHIKO , UESHIMA JUN
IPC分类号： H04N3/233
摘要： In a CRT display horizontal/vertical synchronizing signals (H, V) are separated from a video signal (CVBS) in a synchronizing separation circuit (1). Position information S of a vertical frame is generated on the basis of the horizontal/vertical synchronizing signals in a count-down processor (2) and then converted to corrected vertical frame information W in a function circuit (3). The corrected vertical frame information W is provided to a vertical deflection waveform generator (4) and to a horizontal deflection correction waveform generator (5) to produce a vertical deflection waveform signal (VSAW) and a horizontal deflection correcting waveform signal (E/W). The corrected vertical frame information W may be compared with predetermined voltages (Vref) in comparators (7, 8) to detect an effective frame range in the vertical direction.

2. 发明专利

DE69416043T2 未知
公开(公告)号：DE69416043T2
公开(公告)日：1999-06-24
申请号：DE69416043
申请日：1994-07-04
申请人： SONY CORP
发明人： TAMURA TAKAHIKO , MITO YUMIKO
IPC分类号： H04N5/16 , H04N5/20
摘要： A dark level restoring circuit for a television receiver comprises a video signal source, a pedestal clamp circuit connected to the video signal source and for clamping a pedestal portion of the video signal to a reference pedestal level, a first comparator connected to the pedestal clamp circuit and for comparing the output of the pedestal clamp circuit and a reference dark level, a gain control amplifier connected to the first comparator and for amplifying the output of the first comparator, a synthesizer for synthesizing the outputs of the pedestal clamp circuit and the gain control amplifier, a dark peak hold circuit connected to the synthesizer for holding the dark peak level, a second comparator for comparing the output of the dark peak hold circuit and the reference pedestal level, the output of the second comparator controlling the gain of the gain control amplifier, a blanking signal source, a mute signal circuit for generating a mute signal corresponding to a non-video signal portion when the effective raster size of the video signal is smaller than the size of a face plate of a cathode ray tube to which the video signal is supplied, and a logic circuit for synthesizing the blanking signal and mute signal and for generating a control signal, the control signal controls the gain control amplifier such that the gain of the gain control amplifier is minimum and the dark peak hold circuit such that the holding operation of the dark peak hold circuit is inactive.

3. 发明专利

MY101926A CATHODE RAY TUBE DRIVE CONTROL CIRCUITS. 未知
公开(公告)号：MY101926A
公开(公告)日：1992-02-15
申请号：MYPI19872415
申请日：1987-09-30
申请人： SONY CORP
发明人： TOKUHARA MASAHARU , TAMURA TAKAHIKO
IPC分类号： H04N5/68 , H04N5/59 , H04N9/16 , H04N9/30 , H04N9/64
摘要： A CATHODE RAY TUBE (CRT) DRIVE CONTROL CIRCUIT INCLUDES A FEEDBACK CIRCUIT (4, 5, 12) INTERPOSED BETWEEN A BEAM CURRENT DETECTING CIRCUIT (6 TO 11) AND A SIGNAL PROCESSING CIRCUIT (1) FOR CONTROLLING THE SIGNAL TO BE SUPPLIED TO A CRT (3) IN RESPONSE TO A DETECTED BEAN CURRENT, WHEREBY AT LEAST ONE OF THE CONTRAST LEVEL AND THE BRIGHTNESS LEVEL IS CONTROLLED DEPENDING ON A DETECTED DARK LEVEL. (FIG. 1)

4. 发明专利

DE3430748A1 未知
公开(公告)号：DE3430748A1
公开(公告)日：1985-03-14
申请号：DE3430748
申请日：1984-08-21
申请人： SONY CORP
发明人： TAMURA TAKAHIKO , TOKUHARA MASAHARU
IPC分类号： H04N5/59 , H04N9/30 , H04N9/64 , H04N3/20
摘要： A CRT drive control circuit for automatically limiting beam current when it is too large. A brightness reduction control and a contrast reduction control are alternately applied in accordance with a dark level detection of a video signal.

5. 发明专利

CA2483581A1 VIDEO SIGNAL PROCESSING CIRCUIT AND VIDEO SIGNAL PROCESSING METHOD 未知
公开(公告)号：CA2483581A1
公开(公告)日：2004-09-16
申请号：CA2483581
申请日：2004-02-09
申请人： SONY CORP
发明人： TAMURA TAKAHIKO , NAGAMINE TAKATOMO , UESHIMA JUN
IPC分类号： H04N9/44 , H04N9/64
摘要： In a digital chroma demodulating system, when directly outputting A/D converted composite signals, while switching system clock frequencies to determine the signal format, images to be displayed in accordance with the composite signals are prevented from varying and becoming unsightly due to t he switching of system clock frequencies. As to the system clock frequency (m)( = fsc .times. n) for synchronization with a color burst signal, its coefficien t (n) is changed in accordance with the format (a color burst signal frequency ), thereby confining the system clock frequency (m) for formats within a given range. As a result, a nearly constant sampling frequency can be used to perform A/D conversions of the composite signals, so that sampling condition s such as the sampling frequency and sampling points will not significantly va ry.

6. 发明专利

DE69416043D1 未知
公开(公告)号：DE69416043D1
公开(公告)日：1999-03-04
申请号：DE69416043
申请日：1994-07-04
申请人： SONY CORP
发明人： TAMURA TAKAHIKO , MITO YUMIKO
IPC分类号： H04N5/16 , H04N5/20
摘要： A dark level restoring circuit for a television receiver comprises a video signal source, a pedestal clamp circuit connected to the video signal source and for clamping a pedestal portion of the video signal to a reference pedestal level, a first comparator connected to the pedestal clamp circuit and for comparing the output of the pedestal clamp circuit and a reference dark level, a gain control amplifier connected to the first comparator and for amplifying the output of the first comparator, a synthesizer for synthesizing the outputs of the pedestal clamp circuit and the gain control amplifier, a dark peak hold circuit connected to the synthesizer for holding the dark peak level, a second comparator for comparing the output of the dark peak hold circuit and the reference pedestal level, the output of the second comparator controlling the gain of the gain control amplifier, a blanking signal source, a mute signal circuit for generating a mute signal corresponding to a non-video signal portion when the effective raster size of the video signal is smaller than the size of a face plate of a cathode ray tube to which the video signal is supplied, and a logic circuit for synthesizing the blanking signal and mute signal and for generating a control signal, the control signal controls the gain control amplifier such that the gain of the gain control amplifier is minimum and the dark peak hold circuit such that the holding operation of the dark peak hold circuit is inactive.

7. 发明专利

GB2199208B OSCILLATOR CIRCUITS 未知
公开(公告)号：GB2199208B
公开(公告)日：1990-09-26
申请号：GB8727615
申请日：1987-11-25
申请人： SONY CORP
发明人： TAMURA TAKAHIKO , SUZUKI HIROYUKI
IPC分类号： H04N3/27 , H03K3/0231 , H03L7/099
摘要： Oscillation circuit that generates an oscillating signal by charging and discharging a capacitor between two reference voltages employs several constant current sources, with the number of constant current sources that are connected to the capacitor at any one time being controlled so that the oscillation frequency can be changed in a step-wise fashion, whereby the circuitry is relatively simplified compared with known step-wise changing oscillators.

8. 发明专利

GB2199208A OSCILLATOR CIRCUIT 未知
公开(公告)号：GB2199208A
公开(公告)日：1988-06-29
申请号：GB8727615
申请日：1987-11-25
申请人： SONY CORP
发明人： TAMURA TAKAHIKO , SUZUKI HIROYUKI
IPC分类号： H04N3/27 , H03K3/0231 , H03L7/099 , H03L7/24 , H03K3/03
摘要： Oscillation circuit that generates an oscillating signal by charging and discharging a capacitor between two reference voltages employs several constant current sources, with the number of constant current sources that are connected to the capacitor at any one time being controlled so that the oscillation frequency can be changed in a step-wise fashion, whereby the circuitry is relatively simplified compared with known step-wise changing oscillators.

9. 发明公开

EP1524863A4 VIDEO SIGNAL PROCESSING CIRCUIT AND VIDEO SIGNAL PROCESSING METHOD 审中-公开
标题翻译：视频信号处理电路和视频信号处理
公开(公告)号：EP1524863A4
公开(公告)日：2005-11-02
申请号：EP04709327
申请日：2004-02-09
申请人： SONY CORP
发明人： NAGAMINE TAKATOMO , TAMURA TAKAHIKO , UESHIMA JUN
IPC分类号： H04N9/44 , H04N9/64
CPC分类号： H04N9/44 , H04N9/642
摘要： In a digital chroma demodulating system, when directly outputting A/D converted composite signals, while switching system clock frequencies to determine the signal format, images to be displayed in accordance with the composite signals are prevented from varying and becoming unsightly due to the switching of system clock frequencies. As to the system clock frequency (m)(= fsc x n) for synchronization with a color burst signal, its coefficient (n) is changed in accordance with the format (a color burst signal frequency), thereby confining the system clock frequency (m) for formats within a given range. As a result, a nearly constant sampling frequency can be used to perform A/D conversions of the composite signals, so that sampling conditions such as the sampling frequency and sampling points will not significantly vary.

10. 发明授权

EP0503915B1 Correction signal generating circuit for television receiver 失效
标题翻译：电路，用于为电视接收机产生一个校正信号
公开(公告)号：EP0503915B1
公开(公告)日：1997-12-29
申请号：EP92302063
申请日：1992-03-11
申请人： SONY CORP
发明人： MIYAZAKI SHINICHIROU , MURAKAMI KYOICHI , TAMURA TAKAHIKO , MURAYAMA HIROSHI
IPC分类号： G09G1/04 , G09G1/00 , G09G1/16 , H04N3/16 , H04N3/233 , H04N3/27 , H04N3/23
CPC分类号： H04N3/2335

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式