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    • 3. 发明申请
    • CHIP EQUALIZER AND EQUALIZING METHOD
    • 芯片均衡器和均衡方法
    • WO2008018736A1
    • 2008-02-14
    • PCT/KR2007/003788
    • 2007-08-07
    • SK Telecom Co., Ltd.LEE, Goon SeopLEE, Dong HahkYU, Jae HwangIHM, Jong TaeOH, Se Hyun
    • LEE, Goon SeopLEE, Dong HahkYU, Jae HwangIHM, Jong TaeOH, Se Hyun
    • H04L27/01
    • H04L25/03038H04L1/0045H04L1/0065
    • Disclosed are a chip equalizer and an equalizing method capable of minimizing complexity for signal demodulation in accordance with performance of a receiver. The chip equalizer comprises a delay control module that recognizes an area having a main signal included therein from a signal distribution of signals received from a tuner and determines a noise compensation area in accordance with a delay difference between neighboring main signals; at least one first unit delay module that delays, among the signals received from the tuner, a signal of the area having the main signal included therein at an interval of a chip unit and outputs it to a tap co¬ efficient estimation module; and at least one second module that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit.
    • 公开了一种能够根据接收机的性能使信号解调的复杂度最小化的码片均衡器和均衡方法。 芯片均衡器包括延迟控制模块,其从包括从调谐器接收的信号的信号分配中识别其中包含主信号的区域,并且根据相邻主信号之间的延迟差确定噪声补偿区域; 至少一个第一单元延迟模块,在从调谐器接收的信号中,以芯片单元的间隔包含其中包含主信号的区域的信号,并将其输出到抽头有效的估计模块; 以及至少一个第二模块,其在从调谐器接收的信号中,以芯片单元的间隔包含其中不包括主信号的区域的信号。